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The Dawn of a New RISC

The Dawn of a New RISC
by Camille Kokozaki on 06-01-2018 at 7:00 am

The 8[SUP]th[/SUP] RISC-V Workshop was held in Barcelona May 7-10 with 325 attendees from 150+ companies and was the biggest RISC-V event outside of Silicon Valley, demonstrating the momentum of the RISC-V Foundation and the growth of the ecosystem in Europe.

Member companies announced new solutions, partnerships, and participated in the workshops with presentations and active networking and exchange of information as befits an open-source organization committed to the common good and continuing RISC technology progress.

Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC) co-hosted the Workshop, and NXP and Western Digital co-sponsored the successful event.

21742-barcelona-workshop.jpg
In this introduction, a summary highlight of what RISC-V is, why it is important to stay abreast of what is becoming a wave to catch, a play to match, a plot to hatch, a plane to catch, a script to batch. I have beaten to death the mixed metaphors and aspiring song lyrics, so let us just dive in. I will draw heavily from published presentations at the workshop and from prior open source content from enthusiasts fueling this emerging community with a coordinated attempt at multi-organization rewriting/recoding of what RISC was and is intended to be. Regular upcoming postings will be featured. But first things first.

What is RISC-V?
Krste Asanovic (UC Berkeley, RISC-V Foundation & SiFive) summarized RISC-V in his state of the Union as:

  • A high-quality, license-free, royalty-free RISC ISA specification originally from UC Berkeley
  • A standard maintained by non-profit RISC-V Foundation
  • Suitable for all types of computing systems, microcontrollers to supercomputers
  • With Numerous proprietary and open-source cores
  • Experiencing rapid uptake in industry and academia
  • Supported by a growing shared software ecosystem
  • A work in progress…

He went on to say that the Modest RISC-V project goal was to become the industry-standard ISA for all computing devices.While declaring that all was looking great, he acknowledged that a lot of work is left to do.

In the drive for standardization and compliance, the RISC-V value is to provide a free and open ISA standard to connect hardware and software with simultaneous allowance for standards and customization, aiming to prevent fragmentation and enforcing RISC-V compliance processing. The foundation went about selecting actual instructions required for given certification, fixing holes and ambiguities and came up with an encoding terminology classifying Standard (defined by the Foundation), Reserved (for future standard extensions) and Custom (implementer-specific extensions) fields.

RISC-V has a big tent philosophy in that it enables all types of RISC-V implementation from 32-bit microcontrollers with 1KB SRAM or 64-bit Unix servers all the way to 128-bit 100,000 core supercomputers. It ranges from fully open-platforms with only open-source software to fully locked down platforms, completely trusted software. The benefits are maximum reuse with reusable ISA and software modules.

RISC-V compliance is two-fold:

  • ISA compliance occurs if it runs claimed RISC-V unprivileged code correctly and on any platform (noting that tiny platforms with 1KB SRAM are a challenge) and with similar Foundation ISA compliance tests.
  • Platform compliance occurs with tight constraints on system configuration and options to support a software ecosystem and interfaces between platform hardware and platform hardware. Though privileged architectures can vary widely across platforms (timers, memory maps, security, hypervisor), unprivileged ISA choices are constrained by the need to reuse compiler/library work.
  • The sentiment stated at the conference by Krste was that RISC-V Adoption was no longer if, but where and when.360(Mainframe), x86(PC), ARM (smartphone)will likely remain as incumbent architectures in their markets but everything else is open to RISC-V (Data Centers, AI, automotive, healthcare, industrial, IoT among many other use cases).

From the standpoint of coordinating and orchestrating the execution the Board of Directors has created 3 standing committees: Marketing, Technical and Security (new). They will oversee various task groups with specific assignments (debug, crypto, events and so on).

Why RISC-V?
1. Growing Acceptance: 150+ companies and increasing

21742-barcelona-workshop.jpg

2. Commercial Grade RISC-V Ecosystem Building on Open Source Toolchains (IDE, Trace Debug, RTOS)
3. Large companies and startups alike are building RISC-V SoCs and PoCs
4. Advantages in Security and Power
5. Standard Open Source yet user extendable for differentiation and energy saving
6. Simple and far smaller than other commercial ISAs
7. Clean-slate design
[LIST=|INDENT=1]

  • Clear separation between user and privileged ISA
  • Avoids μarchitecture or technology-dependent features

    8. Modular ISA designed for extensibility/specialization
    [LIST=|INDENT=1]

  • Small standard base ISA, with multiple standard extensions
  • Sparse and variable-length instruction encoding for vast opcode space

    9. Stable
    [LIST=|INDENT=1]

  • Base and standard extensions are frozen
  • Additions via optional extensions, not new versions
  • Developed with leading industry/academic experts and software developers

    Upcoming blog postings will highlight some of the hardware and software being developed by the ecosystem, will describe some of the task group activities, additional highlights of the workshop and other relevant information and knowledge and awareness of RISC-V progress so stay tuned.

    Resources

    Recap of the Barcelona workshop including proceedings, product announcements, media coverage, mailing lists.

    21742-barcelona-workshop.jpg


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