How Arteris is Revolutionizing SoC Design with Smart NoC IP

Recently, Design & Reuse held its IP-SoC Days event at the Hyatt Regency in Santa Clara. Advanced IP drives a lot of the innovation we are seeing in chip design. This event provides a venue for IP providers to highlight the latest products and services and share a vision of the future. IP consumers are anxious to hear about all the new technology conveniently in one place. Some of the presentations rose above the noise and made a substantial impact. This is a story of one of those presentations. Read on to see how Arteris is revolutionizing SoC design with Smart NoC IP.

Who’s Talking?

 The presentation was delivered by Rick Bye, director of product management at Arteris. He also developed the content with Guillaume Boillet, senior director of strategic marketing at Arteris. These folks bring a lot to the table when it comes to advanced chip design.

Besides Arteris, Guillaume Boillet has worked at Synopsys, Mentor, Atrenta, ST-Ericsson, STMicroelectronics, and Thales.  He has substantial experience in hardware design and EDA tool development and marketing with a focus on power optimization and connectivity. The skills he brings to Arteris are well-suited to the company’s broad footprint.

Before joining Arteris, Rick Bye had a long career in the development of chips and IP for advanced communications and power management at companies such as Texas instruments, Broadcom, Zarlink Semi, Silicon Labs, NXP, and Arm. The combined knowledge and experience of these two gentlemen is formidable. The content developed and delivered at IP-SoC Days reflected that experience. A link is coming for the presentation but first let’s look at the topics covered.

What Was Discussed

Rick began with an overview of who Arteris is and where the company touches the semiconductor ecosystem. His first slide is an eye-popping overview of technical accomplishments and ecosystem impact. Once you click on the link below, you’ll get to see the incredible array of logos touched by Arteris.

In terms of corporate resume, there are also a lot of impressive statistics to review. Most folks know that Arteris is a system IP company. Some facts you may not know is that the company can claim 3.7B+ SoCs shipped in electronic systems, with 200+ active customers, and 850+ SoC design starts. The company’s products are used by 9 out of the top 10 semiconductor companies and the company has a 90%+ customer retention rate. There are plenty more accomplishments cited.

In terms of footprint, the focus is on overcoming complexity with maximum flexibility for optimized SoCs.  There are three parts of this story, SoC Integration Automation, Network-on-Chip (NoC) Interconnect IP, and Network-on-Chip Interface IP. The balance of the presentation focused on the second item and how Arteris impacts design in this area. Regarding NoC usage, it was reported that there are typically 5-20 NoCs per chip or chiplet with NoCs representing 10-13% of the silicon.

The next section of the presentation examines semiconductor market dynamics. The emerging trends and the impact of AI are always interesting to hear about, and there are some great statistics presented. For those who have been in this industry for a while, you will be familiar with the projections made by Handel Jones at IBS. You will get to see Handel’s latest numbers, which are always interesting.

The next part of the presentation focuses on Arteris Smart NoC technology. There are two families of products here. Ncore delivers the requirements for cache-coherent interconnect IP, and FlexGen, FlexNoC, and FlexWay serve the needs for non-coherent Interconnect IP.  The remainder of the presentation focuses primarily on the needs of the non-coherent portion of the design.  The figure below illustrates where the non-coherent interconnect IP products fit.

FlexGen impacts a broad range of applications, so more details are presented on this technology. The graphic at the top of this post presents some of those details. To provide more context, here are some additional facts:

Challenge: SoC design complexity has surpassed manual human capabilities, requiring smart NoC automation. Modern SoCs have 5 to 20+ unique NoC instances and each instance can require 5-10 iterations.

FlexGen, smart NoC IP from Arteris delivers:

• Productivity Boost: Accelerates chip design by up to 10x, shortening and reducing iterations from weeks to days for greater efficiency
• Expert-Level Results: Enhances engineering efficiency by 3x while delivering expert-quality results with optimized routing and reduced congestion
• Wire Length Reduction: AI-driven heuristics reduce wire length by up to 30%, improving chip or chiplet power efficiency

Connects any processor (Arm, RISC-V, x86) and supports industry protocols.

The presentation then dives into more detail about FlexGen and how it builds on FlexNoC technology for physical awareness. The core 80+ patent profile of Arteris in this area is explored and specific examples of performance and efficiency advantages are presented. The workflows involved are presented, along with specific examples of its impact.

To Learn More

I’ve just scratched the surface in this overview. You need to watch the complete presentation from IP-SoC Days to get the full picture of how Arteris can help with your next design. You can access a video of the complete presentation here. And that’s how Arteris is revolutionizing SoC design with Smart NoC IP.

Also Read:

Is Arteris Poised to Enable Next Generation System Design?

Arteris Raises Bar Again with AI-Based NoC Design

Arteris Raises Bar Again with AI-Based NoC Design

MCUs Are Now Embracing Mainstream NoCs