Jade Design Automation’s Register Management Tool

When more than one person is working on any project, coordination is imperative. When the team size grows, being in sync becomes essential. When it comes to SoC design management, registers and bit fields are used to communicate status of results and execute conditional controls. The Register Management function plays an essential role during the course of any modern day SoC product development. Earlier this year, SemiWiki introduced Jade Design Automation (JadeDA) to its readership, through an interview with its CEO and Founder, Tamas Olaszi.  JadeDA is focused on register management of a chip design starting from the system architecture stage all the way to software bring-up.

This post will discuss register management and a feature to configure RISC-V processor registers. JadeDA will be showcasing their Register Manager tool at the upcoming DAC 2022 in San Francisco. I had an opportunity to chat with Tamas and this blog is based on that conversation.

Register Management Benefits

Where

While register management has always been important on any chip design project, it takes more importance in today’s world of hardware/software co-design/co-development. Even an average complexity chip could include 100,000 or even millions of registers. During the design phase, bit fields in those registers could be change frequently, even many times in a day. This necessitates the validation, regeneration of RTL, updating of UVMs and the relevant documentation in close to real-time as possible. Without register management, different teams could be out-of-sync. For example, a change made by the design team may not be noticed by the verification team right away.  The software team may be working off of outdated information, wasting cycles on developing code that would need to be changed.

Following is a real life example that Tamas narrated during our chat. It was an embedded software development project. The documentation the team was working off of said to set certain bits and then wait for certain things to happen and then perform some actions. The hardware team knew when that something happens because they have access to an internal register. But the software team doesn’t have access to this register. No status bits or interrupts were triggered. Without knowing, the software could be waiting forever to take action. This is the kind of thing that can happen if there is no centralized information access that all teams could review, verify and work from.

While the above example is from an embedded real-time device application, the same goes for any device including HPC-oriented high-performance application. Only difference is, we can expect even more frequent updates the larger and more complex a design gets. And the speed at which the centralized information gets updated and all relevant code and documentation gets regenerated becomes critical.

Who

A good register management capability will render the following functional roles the respective benefits. It also allows automated broadcast of updated information to all the different teams working on a project.

• System architects can capture and maintain all the high level system information in a centralized way.
• System Integrators can pull together IPs from various sources to a centralized platform for enhanced quality.
• IP teams can auto-generate production ready RTL and UVM register descriptions throughout the development process, which is a great productivity booster.
• Engineering Managers can monitor the consistent and high quality release deliverables offered to their internal or external customers.
• Software Engineers can have register information loaded into their debuggers so they can instantly see what register they are working with on a particular offset; they can do this without having to wade through pages of documentation.

JadeDA’s Register Management Tool

JadeDA has kept it simple and straightforward by naming their register management tool, the Register Manager. The tool efficiently manages all tasks around the HW/SW interface of an SoC. Users can capture register and bitfield information at the IP level as well as the memory maps on the IP, subsystem and SoC level. The Register Manager generates RTL, Verification, SW, Documentation and data Interoperability formats like IP-XACT 1685-2009 and 1685-2014 from these descriptions.

Data Model and Flexibility for Customization

While data models can be based off of standards such as IP-XACT and SystemRDL, standards evolve very slowly. A proprietary data model from a supplier with strong support for customization serves customers well. JadeDA’s importing tools can migrate IP-XACT and SystemRDL based data models. Data models/tools based off of IP-XACT usually have vendor extensions. JadeDA tool’s data model is richer than what IP-XACT offers. Legacy data in custom formats can be imported via the tool’s API. The API is very efficient and well documented. JadeDA can also easily import register information stored in excel sheets.

GUI

The Register Manager has a rich and intuitive GUI to visualize and edit the HW/SW interface and edit the register and bitfield information. The GUI is much more than just entry fields for various attributes. It can be controlled with mouse only to change attributes like offsets, widths, access types and reset values. There is also a full keyboard support with intuitive focus traversal that allows quick and efficient data capture without raising the hand from the keyboard. Typing pre-existing information from a PDF document can be done without having to reach for the mouse in-between keyboard entries. This is a productivity enhancement.

Note: The tool also has a fully functional shell mode for power users as well as fully scriptable command files for automated flows.

Performance

As changes happen in a design, the tool can capture the data, validate it and generate RTL, UVM, documentation, software and IP-XACT collateral in a few seconds. Jade DA has noticed that its tool runs in an order of magnitude less time than what is available in the marketplace today. And the performance of JadeDA tool scales linearly.

Processor Registers Configurability Feature

JadeDA will be showcasing this new feature of the Register Manager tool at DAC 2022.

JadeDA can deliver its customers the superset of control and status registers (CSRs) through the tool’s GUI. As the customers configure their designs, they can get rid of the CSRs they don’t need for a particular design. A RISC-V based design serves as a good case study. The RISC-V specification offers a whole bunch of CSRs, not all of which are used by all customers. And different customers or different projects at the same customer may use different selection of CSRs. The tool captures all of the registers in all the details contained in the RISC-V specification. With the configurability feature, users can configure the particular subset they need. Some of the configuration options are available as RTL configurable parameters. If the customer turn them off, the users won’t be able to configure the corresponding registers.

This configurability feature is something that JadeDA can implement in its tool for any processor architecture/ISA. Contact JadeDA to explore.

You have to see the live demo to fully appreciate the power of the tool, the user interface and ease of use. See the Register Manager Tool Demo @Booth Number 2430 at DAC 2022 in San Francisco.

Meanwhile, here are some screenshots from the tool. The following two Figures show the scenarios of when a FPU and corresponding registers are included in the configuration and when they are not.

The following Table shows the supervisor related CSRs found in the RISC-V specification.

The following relates to a case of an application processor where supervisor related CSRs are needed. The screenshot below shows their conditional presence being enabled.

See the Register Manager Tool Demo @Booth Number 2430 at DAC 2022 in San Francisco.