Events EDA2025 esig 2024 800X100
WP_Term Object
(
    [term_id] => 50
    [name] => Events
    [slug] => events
    [term_group] => 0
    [term_taxonomy_id] => 50
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1307
    [filter] => raw
    [cat_ID] => 50
    [category_count] => 1307
    [category_description] => 
    [cat_name] => Events
    [category_nicename] => events
    [category_parent] => 0
)
Events
Posted on by Daniel Payne

Robustness, Reliability and Yield at DAC

Robustness, Reliability and Yield at DAC
by Daniel Payne on 06-26-2012 at 8:15 pm
Categories: EDA, Events

On Wednesday at DAC I met with Bob Slee, distributor and Michael Siu, AE for MunEDA to get an update on what’s new. MunEDA has EDA software for:

  • Schematic porting
  • Nominal circuit analysis
  • Nominal circuit optimization
  • Statistical circuit analysis
  • Statistical circuit optimization
  • IP porting
  • Circuit model generation

More important than just EDA tools they have tier one semiconductor customers using these tools.

Notes

Users: AMS designer, IP design, custom, memory – use Wicked to help optimize a netlist. User will define which transistors to change or vary, then tool will invoke SPICE circuit simulator, measure results. Specify: W, L, VDD or even process parameters.

Example: OpAmp circuit with a required gain. Wicked will optimize to try and reach the goal. If it cannot reach that spec it tells you.

WICkeD works with: Spectre, HSIM, Eldo, etc. simulator indepedent.

WICked: About 10 years old. From Technical University of Munich, help from Infineon.

Customers: Samsung, Toshiba, Hynix, ST, Infineon, ON Semi, ST, Altera, Faraday, Bosch, Atmel, IR, Fraunhofer, X Fab, Dialog Semi.

Sales: Contact your representative.

Time based license.

WiCkeD – Worst Case Distance for optimization.

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