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3D Thermal and Mechanical Stress for IC Packaging

3D Thermal and Mechanical Stress for IC Packaging
by Daniel Payne on 06-19-2012 at 8:02 pm

3D has been a growing buzz word in IC design and packaging for several years now, so it’s refreshing to actually find an EDA vendor that has developed tools to help analyze something like 3D thermal and mechanical stress at DAC. I met with Jens Andersen, CEO of Invarian to learn more, although my only mistake was that every few minutes a colleague or prospect would stop by and say hello to Jens and interrupt us. The Invarian booth had visible traffic that kept the staff engaged.


What’s New in 2012 since last DAC?
Offer Dynamic Power, Dynamic Thermal, 3D Thermal, 3D Mechanical Stress (or 2.5D with interposer).

InVar Frontier 3D – new for 2012, 3D thermal and mechanical stress. Early release for mechanical stress, while 3D thermal in production. $150K for a one year term license.

In 2011 released Pioneer Platform – IR, EM, Thermal, Power for AMS designs. Not trying to compete on STA or dynamic timing against major EDA tools.

Customers – Telecom, cell phone handset, power, stealth, IP for Flash Memory.

Si2 has a 3D working group, InVarian is a member of that (Mentor, TI, Qualcomm, Apache, Atrenta).

12 people in the company, private funding, avoiding VC.

HQ is Santa Clara.

Previous products – InVar Pioneer SoC for thermal analysis of AMS. Largest design was 50 million cells, so capacity is there for 40nm and results of Power were within 1% of dynamic results. Present customer at 28nm and 100 million cells using Pioneer SoC.

Pioneer Digital – subset of Pioneer SoC, just digital. $60K

Pioneer Analog – subset of Pioneer SoC, just analog. $60K

Pioneer SoC – $160K full package.

GUI – Choose: IR, EM, Thermal, Power.

Cell-level analysis, where libraries are created by the tool.

TSMC – not qualified in any flow yet, so stay tuned.

Inputs – Library (LEF, Liberty)
– Design Data (DEF, Verilog)
– Timing Constraints (SDC)
– SwitchingActivity (SAIF, VCD)
– Parasitics (SPEF)
– Technology (ITF)
– Power Architecture (UPD, CPF)
– Thermal Model (Tcl commands, packaging specs)

GUI – own version, plus Tcl command line, interactive or batch modes. Can view the layout hierarchically to identify hot spots.

DAC 2013 – More customers for the 3D product, more silicon proof of the accuracy results. Market adoption with good support. Moving up stream for prototyping methodologies, for quicker and earlier analysis, closer to logic synthesis, even power estimations.

Evaluations – contact the factory at Most evaluation length take one to two months. Using Webex to communicate with Japanese clients now, that’s different than before where a physical trip was required.

Learning – only a few hours, proficient within one week, reports help you tune your design to meet specs..

Tool users – physical designers, IC designers, SI and PI designers. Because the tool can be run in hours you can iterate more often to get results sooner than before.

Runtime requirements – multi cpu machines, for 30 million instances you use about 110GB of RAM on a 32 CPU machine, linear RAM usage. Linear usage up to 64 CPUs.

If you announce a new product before DAC like Frontier 3D and then don’t have it shown anywhere on your web site, then that kind of tells me that it’s way too soon to start talking about it. Credibility is built with customer quotes.

For thermal analysis another EDA vendor is Gradient DA.

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