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Events
Posted on by Daniel Payne

Fast Monte Carlo and Analog Fast SPICE

Fast Monte Carlo and Analog Fast SPICE
by Daniel Payne on 06-08-2012 at 10:25 am
Categories: EDA, Events

Britto Vincent of ProPlus Design Solutions met with me at DAC on Monday morning to talk about Design For Yield (DFY) and Analog Fast SPICE.

In 2011 ProPlus announced DFY tools where the technology came from IBM, it provides fast Monte Carlo results up to 3 sigma, then added NanoSpice for faster simulation results. Similar in approach to Solido but with our own SPICE tool. High sigma analysis is useful in memory designs. Statistical simulation with yield analysis is accomplished using NanoYield. We had a joint presentation with IBM on Tuesday at DAC, IBM did a paper on Sunday too.

History of where ProPlus cam from – Started out as BTA, then Celestry, Cadence acquired Ultrasim, 2006 spun out from Cadence. We’ve been doing device modeling since 1991 (BTA).

In the Lab we can perform noise analysis.

Our own SPICE tool is called NanoSpice (like FineSim Pro). The simulator is both hierarchical and parallel. You can simulate a DRAM with up to 550M elements, or an SRAM with up to 65M elements.

The customers of NanoSpice cannot be mentioned yet, although we have a memory IDM and a southern CA client.

Device Modeling is done with the BSIMProPlus tool, and it is used by foundries and IDMs to create new models. This has been our core business.

NanoSpice is our Analog Fast SPICE circuit simulator and it can accept Spectre, HSPICE and Eldo format. The output is with FSDB so you can use a standard wave form viewer from companies like SpringSoft (Novas). Foundry qualification is in process now for NanoSpice.

For high sigma analysis our approach has been qualified with IBM (implied qualification with Common Platform).

We have offices in Japan, Shanghai, San Jose, Beijing and Taiwan.

NanoSpice is about 5X to 10X faster than HSPICE, Spectre, FineSim SPICE. Not a FastSPICE simulator and it’s similar to the BDA simulator. We are faster than Cadence APS. Co-simulation not supported yet, just pure SPICE netlist. We do support Verilog A.

We have about 100 people now and are privately funded.

12 months from now we expect more customer adoption in DFY and SPICE simulation.

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