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DVCon: Formal Verification with lunch

DVCon: Formal Verification with lunch
by Paul McLellan on 02-03-2012 at 6:03 pm

 At DVCon on Thursday March 1st (St David’s day for any Welsh readers) Jasper is sponsoring lunch from 12pm to 1.30pm. It will take place in the Cascade/Sierra ballrooms.

During lunch there will be a panel discussion Formal Verification from Users’ Perspectives with real users no how they mitigate risk in their designs while meeting the tight schedules of modern designs. The panel will share their experiences with formal verification and how the formal approach has helped them in different ways in their design and verification methodologies.

The panelists are:

  • Jon Michaelson from nVidia
  • Ambar Sukar from ParadigmWorks
  • Someone from ARM
  • Probably one other company too

Details of the event are here. There is no need to register although you must be registered for DVCon.

Immediately following the lunch, at 1.30pm in the Siskiyou ballroom, Jasper is running a tutorial Leveraging Formal Verification Throughout the Entire Design Cycle. The tutorial last until 5pm and is conducted by Lawrence Loh and Norris Ip. They will talk about the benefits of using formal technology in such areas as:

  • Stand-alone verification of architectural protocols
  • Designer sandbox testing for RTL development
  • End-to-end data packet integrity
  • SoC connectivity and integration verification
  • Root-cause isolation and full proofs during post-silicon debug

Formal verification can be a valuable addition to traditional verification methods. For example, applying formal techniques early in the design cycle to exhaustively verifying block-level design functionality can produce higher quality RTL delivered to unit and system level verification. Attendees will learn about new formal technologies and flows that enable designers and verification engineers to augment existing flows. Also included will be discussions about how effort applied to one application can be leveraged in others. When applied intelligently, formal technologies can enhance traditional design and verification flows to help reduce the risks associated with increasing SoC complexity.

Details of the tutorial are here. You can add this tutorial to your DVCon pass with tutorials, or even register just to attend this one tutorial. Details of registration are here.

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