Webinar: Faster Debug of Complex Testbenches Using Visualizer
March 5 @ 8:00 AM - 9:00 AM
Wednesday, March 5 – 8:00 AM Pacific
Debugging testbenches can be a time-intensive challenge, but modern tools provide advanced features to simplify and accelerate the process.
This webinar will explore essential capabilities such as basic line stepping, dynamic variable monitoring, constraint debugging, and UVM topology visualization.
Attendees will learn how to effectively identify and resolve issues in complex testbenches, streamline workflows, and enhance overall verification efficiency.
Discover practical techniques and tools to improve productivity while navigating the increasing complexity of today’s designs.
What You Will Learn:
- Debugging complex testbenches
- Constraint debugging
- UVM debug and visualization
- Dynamic variable monitoring
Who Should Attend:
- Verification engineers who use QuestaSim and Visualizer
Products Covered:
- Visualizer, QuestaSim
Speaker:
Erik Jessen
Product Engineer in the Digital Verification Technologies, Siemens EDA
Erik Jessen is a Product Engineer in the Digital Verification Technologies division at Siemens EDA, focused on Aerospace & Defense.
He has worked on designs from RF/analog to systems engineering and FA, in a range of products including medical, nuclear, consumer, and A&D. With experience in DO-254 and DO-178 to DAL-A level.
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