Masterclass: Microsoft Focus on IP QA with Solido IP Validation Suite

As System-on-Chip (SoC) designs grow increasingly complex, design IPs have become essential building blocks, promoting modularization and reusability. However, ensuring quality across vast IP libraries with diverse formats and views presents a significant challenge. Inconsistencies such as mismatched data between logical and physical views, missing or extra pins, or incompatible timing models can lead to costly errors if not detected early. Addressing these issues during the initial stages of the design process is critical to meeting production timelines and delivering superior silicon quality. Additionally, unexpected changes between different versions of the same IP, such as modified layouts, altered timing parameters, or variations in format compliance, add further complexity, emphasizing the need for a robust framework to manage these challenges effectively.

Join this Masterclass and learn how Microsoft leverages Solido IP Validation Suite to build and implement a robust IP QA framework. Discover how this approach enables:

– Early identification of IP quality issues, saving valuable engineering time.
– Cost savings by avoiding late-stage engineering change orders (ECOs).
– Enhanced IP quality metrics, ensuring seamless production and integration flows.

Topic Include:

– Challenges of managing quality across internal and third-party IPs
– Developing a unified QA solution across teams and programs
– Addressing inconsistencies across formats such as .LIB, Verilog, SDF, LEF, and DEF, and version-to-version inconsistencies
– Examples of how the Solido IP Validation Suite optimizes workflows and enhances IP quality

Featured Products:  Solido IP Validation Suite