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DVCON 2025 US

February 24, 2025 - February 27, 2025

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DVCON U.S. 2025

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees to adopt similar techniques to improve their own design and verification flows.

Call for Submissions

The Design & Verification Conference is looking for submissions for the in-person 2025 Conference and Exhibition. This conference focuses on the practical aspects of design and verification of electronic systems and integrated circuits. This could be applications of languages, tools, methodologies, and/or standards. This could be your chance to help the industry we are all a part of.  For those familiar with DVCon, the submission timeline has changed for this year. Please see below for more details.

DVCon honors the Sutherland Best Paper and Best Poster submissions. The awards will be selected by the attendees at DVCon, based on the quality of both the paper and the presentation. So please submit your abstract and join DVCon U.S. 2025!

By submitting this proposal, you are committing to personally attend the conference and deliver the material if it is accepted. Should you be unable to attend in person, it is required that you give a minimum of 4 weeks’ notice before the conference begins to enable the technical committee time to arrange a replacement. Failure to provide adequate notice will result in your inability to propose a paper for the next two years.

REGISTER HERE

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Details

Start:
February 24, 2025
End:
February 27, 2025
Event Tags:
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Website:
https://dvcon.org/

Venue

DoubleTree by Hilton Hotel San Jose
2050 Gateway Pl
San Jose, CA 95110 United States
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