Prevent and Eliminate IR Drop and Power Integrity Issues Using RedHawk Analysis Fusion

I had the opportunity to preview an upcoming SemiWiki webinar on IR drop and power integrity. These topics, all by themselves, have real stopping power. Almost everyone I speak with has a story to tell about these issues in a recent chip design project. When you combine hot topics like this with a presentation that details the collaboration between Synopsys and ANSYS to solve them, you have a real winner in my view. The details of how industry-leading extraction and analysis tools from ANSYS are tied to industry-leading implementation tools from Synopsys are clearly worth a look.

You can view this webinar on Tuesday, March 31, 2020 at 10AM Pacific time. Mark that on your calendar. The registration link is included, above.  I’ll repeat it later. Let’s first review who’s presenting at this webinar and what they’ll cover.

The first speaker is Rahul Deokar, director of marketing and business development for the Synopsys Fusion Design Platform, with focus on signoff products, including RedHawk Analysis Fusion. Rahul begins his presentation with a review of the technology trends and associated challenges and dangers presented by things like dynamic voltage drop and power integrity. He then presents Redhawk-SC and discusses its capabilities to effectively deal with the problems under discussion.

Rahul then describes RedHawk Analysis Fusion, a two-year project to combine the analysis capabilities of ANSYS RedHawk with the implementation capabilities of Synopsys ICC II/Fusion Compiler. Signoff quality analysis with a native integration to an industry-leading implementation flow at the block, subsystem and full-chip levels. This really got my attention.

Getting into more details, Rahul explains the benefits of block-level signoff accuracy, robust place & route optimization and the ability to access the latest distributed processing capabilities of RedHawk-SC. Rahul then summarizes the added features in the new release of RedHawk Fusion. The list is quite extensive and impressive. He also covers the power integrity design flow that is enabled by RedHawk Fusion. To give you a feeling for the what’s included, I’ll just mention one of the many capabilities covered:

Dynamic Power Shaping: optimizes peak current and reduces dynamic voltage drop via clock scheduling.

All the capabilities presented are illustrated with real design examples, including case studies of a 7nm design. To whet your appetite further, machine learning is also employed in the release.

Marc Swinnen then presents the details of ANSYS RedHawk-SC, their next-generation product for 7nm and below. Marc is the director of product marketing at ANSYS. The next-generation architecture for RedHawk was developed about four years ago and it’s called SeaScape – RedHawk-SC is based on it. Marc explains that the motivation for this new platform was two-fold:

• Address the capacity requirements resulting from the dramatic increase in analysis at advanced nodes
• Extend IR-drop analysis to handle the multi-physics considerations of new effects such as electromigration, inductance and thermal gradients

Marc explains that SeaScape uses the same approach for data organization that is used by big data and artificial intelligence tools. Marc goes on to detail the distributed architecture of SeaScape. The discussion is quite impressive and improvements in speed, capacity and efficiency are substantial. Marc also discusses chip-package co-analysis, a critical item for advanced 2.5 and 3D packaging.

Rahul then presents the results of actual customer designs using RedHawk Fusion. Several application areas, all at advanced nodes and from different parts of the world are covered. The webinar concludes with a Q&A session that shines more light on the types of designs this flow can be used on.

The depth of detail presented during this webinar, along with the unique collaboration of two major design tool suppliers make this webinar a must-see. You can register for the webinar here. Don’t miss this one.

Also Read:

Achieving Design Robustness in Signoff for Advanced Node Digital Designs

Navigating Memory Choices for Your Next Low-Power Design

Hybrid Verification for Deep Sequential Convergence