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Synopsys
Posted on by Paul McLellan

Custom Processors: Webinar

Custom Processors: Webinar
by Paul McLellan on 02-21-2012 at 5:24 pm
Categories: EDA, Synopsys

What is a custom processor? Or Application Specific Instruction-set Processor (ASIP) which is the buzzword which may or may not catch on.

Most programming is done on a processor with a fixed instruction set: think Intel x86 or ARM. Intel or ARM decided on what instructions to include, based on a lot of benchmarking across a wide range of different types of workloads. So there is a sense in which these are lowest common denominator instruction sets. This is clearly a good approach for the microprocessor in your cell-phone or your laptop because they have to run a wide range of workloads too. But if you are designing a processor for a specific application domain, such as decoding MPEG video, then the general solution may be very far from optimal, especially in performance or power or both. Since a major reason to create a special purpose processor is to offload a general purpose processor, then you really need to hit a much better performance/power point to justify the effort. Otherwise why bother?

Synopsys didn’t used to be in the processor business, but they acquired the ARC processor with the Virage acquisition and a flavor of the Lisa processor generator with the CoWare acquisition. There is a lot of technology in a custom processor. So much that you can’t really do it by hand. RTL alone is not enough. After all, a processor is no use without assemblers, linkers, compilers, debuggers. You probably want an Instruction Set Simulator (ISS), a very fast model, so you can develop code in parallel with the initial implementation of the chip containing your processor. If you did this by hand, apart from being too expensive, you wouldn’t have a lot of confidence that the instruction set in the processor matched the ISS and matched the compiler and so on. So the only way to have an ASIP is to have an ASIP generator that starts from a specification of the processor and generates all the other views automatically.

Synopsys has a webinar coming up next week on this topic. It is next Tuesday, February 28th, at 8am (Pacific). The webinar is presented by Drew Taussig, who came to Synopsys by way of CoWare where he was part of the processor designer product team. So he’s been dealing with this area for a long time.

Register here.

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