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# Leakage Current TCAD Calibration in a-Si TFTs

Leakage Current TCAD Calibration in a-Si TFTs
by Daniel Payne on 11-23-2014 at 4:00 pm

about amorphous silicon and how that material is well-suited for designing TFTs. Today I’m following up after watching the archived webinarpresented by Nam-Kyun Tak of Silvaco. After clicking on that link you’ll be brought to a brief sign-up page and then can watch the archived webinar in your web browser. This info is most appropriate for TCAD engineers who want to predict semiconductor behavior while gaining insights before actually fabricating a new technology.
Related – Amorphous Silicon and TFTs

TCAD software models a semiconductor device by solving several coupled, nonlinear Partial Differential Equations (PDEs). Numerical solutions to these equations are solved by using a mesh of points within the device, and finally there is a discretization procedure. Here’s a flow of what happens during TCAD device simulation:

The two TCAD tools used for leakage current calibration are Athenaand Atlas from Silvaco:

Equations of a-SI TFT device behavior are derived for:

• Poisson’s equation
• Carrier continuity
• Drift-diffusion model

Carrier distribution is developed for both the Fermi-Dirac and Boltzmann (default choice in Atlas) distributions.

Fermi-Dirac distribution, Boltzmann distribution

The physical models and parameters are shown for:

• Effective Density of States (DOS)
• Intrinsic Concentration (n[SUB]i[/SUB])
• Band Gap Narrowing (BGN)
• Low Field Mobility Model
• Inversion Layer Mobility Model
• Band-to-Band Tunneling
• Trap-Assisted Tunneling
• Probability of Occupation

Intrinsic Concentration

The actual process and device simulations with Athena and Atlas tools have the following inputs and outputs:

An amorphous Silicon TFT device structure is built using Athena where you can visualize the results of each process step:

Each contribution to the Density of State (DOS) model can be simulated in Atlas:

Drain current can then be plotted versus drain voltage at different gate voltage values based upon the initial DOS values. In the second plot we find the energy level is 1.3 eV where the probability of occupation is 0.5:

Transfer curve of 1st TCAD simulation. DOS, f[SUB]tA[/SUB] and n[SUB]A[/SUB] of 1st TCAD simulation

Further steps in this TCAD calibration using the DOS model include varying the NGA parameter of DOS to change the drain current.

Related – SiC and Si Power Devices

A second TCAD calibration example shows how to vary DOS, f[SUB]t[/SUB] and the current density.

Conclusions

This webinar showed TCAD calibration procedures to vary leakage current in a-Si TFTs using a Density of States (DOS) model, probability of occupation, BBT and TAT models. The accuracy of these models enable a TCAD engineer to analyze the leakage current of a-Si TFT devices. View the complete archived webinar for more details.

Q&A

Q: Can I use this DOS model for P-type devices also?

Yes, you can also model P-type devices.

Q: Can I directly extract DOS parameters from simulation?

No, you can only do this indirectly by using initial DOS parameters.

Q: How do we save the occupation of traps for different voltages?

You can save the occupation of traps with the save and trap commands.

Q: Can we use the a-Si TFT model for tunnel TFT?

The basic calibration concepts are quite similar between these different devices.

Q: Can we see the change of density of state over time?

You have to define the DOS manually, and the parameters manually.

Q: Can I simulate DOS effects?

Yes, with Victory and Atlas tools used together.