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DAC in San Francisco will once again be a can’t miss event for semiconductor professionals seeking to discover the latest developments in EDA solutions that address the wide range of issues encountered in delivering high quality IC products and electronics systems to the market. IC Manage will be exhibiting its latest innovations… Read More
PrimisAI is the premier destination for cutting-edge hardware design automation, offering engineers the ultimate companion with advanced Language-to-Code and Language-to-Verification capabilities. Our interactive AI assistant swiftly addresses complex hardware challenges across the entire design stack, from concept… Read More
At booth #2430, the Easylogic technical support team will guide you through the GTECH design flow, offer in-depth product demos, engage in discussions about your ECO applications, and provide tailored recommendations.
Common feedback from customers is that the ECO flow is cumbersome and requires extensive inter-tool compatibility… Read More
As the Design Automation Conference (DAC) approaches, anticipation builds for what promises to be an exceptional event in San Francisco. Attendees can look forward to perfect weather and a plethora of activities beyond the conference, such as sailing on the bay and exploring the city’s iconic landmarks.
Since its inception… Read More
DAC starts June 24th and I can already feel the buzz of excitement building up as I receive updates from EDA vendors like Keysight EDA. Talking with Scott Seiden, Director Strategic Marketing, Keysight EDA Portfolio, I learned that they have the largest booth on the first floor, now that’s a statement that caught my attention. This… Read More
Introduction of 2.5D and 3D multi-die based products are helping extend the boundaries of Moore’s Law, overcoming limitations in speed and capacity for high-end computational tasks. In spite of its critical function within the 3DIC paradigm, the interposer die’s role and related challenges are often neither fully comprehended… Read More
Prologue
Peter was running late for two reasons. First, he encountered unexpected heavy traffic and arrived ten minutes late for a crucial meeting with a customer to run a compliance test of his new 6G phone design prototyped on FPGAs. This prototype’s success was pivotal, as it could secure a significant purchase order.… Read More
As SoC complexities continue to expand to billions of transistors, the quest for higher levels of design automation also rises. This has led to the adoption of High-Level Synthesis (HLS), using design languages such as C++ and SystemC, which is more productive than traditional RTL design entry methods. In the RTL approach there… Read More
I recently had an eye-opening discussion regarding the phenomena of soft errors in semiconductor devices. I always knew this could be a problem in space, where there are all kinds of high energy particles. What I didn’t realize is there are two trends that are making this kind of problem relevant on the ground as well as in space. The… Read More
Disaggregating LLM Inference: Inside the SambaNova Intel Heterogeneous Compute Blueprint