WEBINAR: Overcome Aging Issues in Clocks at Sub-10nm Designs

We all know that designers work hard to reach design closure on SOC designs. However, what gets less attention from consumers is the effort that goes into ensuring that these chips will be fully operational and meeting timing specs over their projected lifetime. Of course, this is less important for chips used in devices with projected lifespans of a few years, such as cell phones. Yet, aging is a major issue for designs that go into applications that call for many years or even decades of operation. These include medical devices, aerospace, military, automotive, infrastructure and many more. Looking at the list above it should also be clear that many of these applications have implications for human safety. A broken cell phone is one thing, a malfunctioning aviation or automotive control system is quite another.

Verifying that a design meets timing specification, including clock tree skew, slew and jitter across process corners, while difficult, is a well understood process, with tools and methodologies available to support it. Evaluating if a chip has been designed to operate after 10 or 20 years of aging is a far more complex task, but an essential one. Frequently designers resort to guard banding to compensate for future aging effects. However, due to the nature of the processes involved in aging, simply adding timing margin may not be sufficient.

In fact, seemingly disconnected decisions about clock gating methods can  have big effects on how aging manifests in older designs. Infinisim, a leading provider of clock tree analysis solutions, discusses the ins and outs of aging and how it can be minimized and simulated before tape out in a white paper titled “CMOS Transistor Aging and its impact on sub 10nm Clock Distribution”. The clock tree plays a critical role in aging and is a good place to start when looking to minimize aging effects.

The Infinisim webinar Overcome aging issues in clocks at sub-10nm designs will cover the challenges associated with aging, limitations of existing methodologies and provide a strategy to increase aging verification coverage. An advanced clock analysis methodology to minimize the impact of aging through increased verification coverage will be presented. The target audience is clock architects and clock designers and timing verification engineers.

Abstract:
Aging is becoming a severe threat to integrated circuits (IC), leading to field failures as transistor sizes continue to decrease. Aging significantly affects the ability of transistors to maintain their operational characteristics and if not thoroughly analyzed, aging will eventually slow down the device and cause circuit failure. In previous design processes at 32nm, 14nm, and even 10nm, clock aging was relatively easily accounted for by guard banding on frequency, slew rates, and other design parameters. With sub 10nm processes we find this is no longer the case, and now more than ever, designers must ensure proper aging analysis of their clocks and implement design mitigations.

Presenter:
Roy Reyes has over 20 years of experience designing clocks for integrated circuits. He was the clock designer for three major CPU’s and several systems on chip (SOC) at Intel. Roy has a master’s degree from the University of Miami and completed several other engineering graduate classes at Virginia Tech, among other top schools. He has a patent in optical computing and has published papers with the department of defense, applied optics, and SPIE (society for optics and photonics). He has received multiple awards at Intel and while working for the department of defense.

Register Here:  Overcome aging issues in clocks at sub-10nm designs 

Also read:

White Paper: A Closer Look at Aging on Clock Networks

WEBNAR: Challenges in analyzing High Performance clocks at 7nm and below process nodes