WP_Term Object
    [term_id] => 30
    [name] => Fractal Technologies
    [slug] => fractal-technologies
    [term_group] => 0
    [term_taxonomy_id] => 30
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 33
    [filter] => raw
    [cat_ID] => 30
    [category_count] => 33
    [category_description] => 
    [cat_name] => Fractal Technologies
    [category_nicename] => fractal-technologies
    [category_parent] => 157
    [is_post] => 1

How About a Quality-Aware IP Design Flow

How About a Quality-Aware IP Design Flow
by Daniel Payne on 05-28-2014 at 6:18 pm

In the EDA world we use hyphens quite often to describe our technical approaches, like: DFM-aware, Power-aware, Variation-aware. I just read a white papertoday on the topic of Quality-Aware IP Design Flows, written by Fractal Technologies. If your group creates IP or re-uses IP, then there’s always the question about the readiness or quality of each IP block. Shown below is a flow of how cell libraries and larger IP blocks get created by an IP vendor and then used by an SoC designer, along with the checking and validation processes necessary to ensure high quality and reduce re-spins.

Incoming IP Inspection

An incoming IP inspection QA tool should detect any incompatibilities on new IP for your present design flow or self-consistency within the IP blocks. The earlier that you uncover an inconsistency with IP the better, because you don’t want to find an IP block issue during tape-out because of the amount of effort required to re-validate your entire SoC design. Semiconductor IP has many assets that require checking:

  • Databases
  • File formats
  • Design views (logical, physical, simulation, etc.)

The QA tool from Fractal Technologies that provides a GUI-based approach to incoming IP inspection is called Crossfire, and it has a matrix of possible checks for each IP database and file format. Any violations or mismatches may then be graphically highlighted. You can even waive any irrelevant view-mismatches for your particular SoC project as needed in order to reduce the amount of information reported.

Background IP Checking

As cell libraries and IP blocks are used within an SoC project, you should be running IP checks again in context, however they can now be run in the background instead of having to use a GUI. You only need to know if there’s been any mismatch and where it arises.

Automated development and characterization flow, all steps are push-button, QA should also be push-button

The Crossfire tool also supports background operation through the use of a Setup API, where you have dedicated checking scripts written in your favorite language (Python, Tcl, Perl) that can automatically find recently changed databases and then run the required checks. You can integrate QA validation within your design repository, so any views that change in your working copy will run the Crossfire checks when the repository commit procedure runs. With this background IP checking approach you can later view any of the QA validation results using the Crossfire Diagnose tool.

With this background IP checking approach the SoC designers don’t have to perform any manual steps to ensure that QA checking is happening. Only when an automated check fails, does the designer need to take any action and quickly pinpoint the source of the failure using Crossfire Diagnose.


Library and IP QA checks can be run both interactively and in batch modes to ensure the highest design quality, and shortest time to market with the Crossfire tool. If you’re visiting DAC in San Francisco next week, then stop by to see Fractal Technologies at booth #507.

lang: en_US