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Defacto Banner 
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Defacto Technologies
Posted on by Daniel Nenni

WEBINAR: Defacto’s SoC Compiler AI: Democratizing SoC Design with Human Language

WEBINAR: Defacto’s SoC Compiler AI: Democratizing SoC Design with Human Language
by Daniel Nenni on 12-04-2025 at 10:00 am
Categories: Defacto Technologies, EDA, Events

Key Takeaways

  • Defacto Technologies has developed an SoC Compiler AI Assistant that converts natural language descriptions into complete, synthesis-ready SoC designs.
  • The AI assistant allows engineers to build complex multi-subsystem SoCs in under 15 minutes, significantly reducing the time traditionally required for scripting and debugging.
  • Real-time design iteration is facilitated by the assistant, allowing for instant updates to SoC configurations and automatic handling of related changes.
  • Defacto's upcoming webinar will showcase the capabilities of the AI assistant and provide insights on its impact on productivity and design infrastructure.

webinar banner2025 (2)Modern chip design has reached unprecedented levels of complexity. Today’s System-on-Chip (SoC) designs integrate multiple processors, complex memory hierarchies, sophisticated interconnects, and much more. All requiring orchestration using complex EDA tool flows. Months are routinely lost to configuration errors, tool-chain mismatches, and manual stitching of subsystems

While these tools are powerful, they demand deep expertise not just in chip architecture, but in the tools themselves. Design teams spend numerous hours navigating complex interfaces, scripting configurations, and troubleshooting tool-specific syntax. The learning curve is time consuming, the margin for error is high, and the time-to-market pressure continuously.

The emergence of artificial intelligence is fundamentally changing how we get access to the information and use complex tools. What was requiring specialized training and years of experience can now be accessed through natural language conversation. But can this transformation extend to something as complex as chip design?

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What if you could skip most of that and simply describe—in plain English—what you need?

Defacto Technologies believes the answer is now “yes.” Their new SoC Compiler AI Assistant turns natural-language conversations into complete, synthesis-ready SoC designs in a fraction of the usual time.

The Defacto AI assistant interoperates seamlessly with both commercial and open source LLMs to leverage natural language queries and help building pre-synthesis complex SoC designs with a significant decrease in design cycles. This AI assistant is open for non-design experts to generate complex pre-assembled subsystems and top level SoCs ready for implementation and verification.

Because the assistant sits on top of Defacto’s production-grade integration engine (already used by tier-1 semiconductor companies), the output isn’t a rough prototype or “AI hallucination”. It’s the same quality you would get from a senior integration team.

This dramatically lowers the expertise barrier. Architects can explore trade-offs without waiting for integration engineers. Junior designers become productive in few days. Entirely new players, startups, even systems companies that previously outsourced chip design, can now create custom silicon in-house.

Join Defacto’s upcoming webinar on Tuesday, December 9, 2025 at 10:00 AM PST and see it for yourself.

This isn’t just theory or slides, you’ll see how:
  • Building an SoC using conversational natural language
  • Real-time design optimizations through simple dialogue
  • Integrating Defacto’s SoC Compiler AI into internal development environments

CEO & CTO Chouki Aktouf will explain the architecture and vision, while R&D engineer Hugo Brisset performs a live, no-slides, no-safety-net demonstration: building a production-grade SoC from a blank project using only voice and natural language, integrating it into a standard EDA environment, and performing on-the-fly optimizations, all in real time.

Attendees will leave understanding:
  • How natural language actually drives industrial-strength EDA tools today
  • Measured productivity gains and remaining limitations
  • What infrastructure you need to deploy this in your own flows

If you’re a chip architect wondering whether AI is still hype, an engineering manager fighting tape-out schedules, or a technical decision-maker evaluating next-generation design platforms, this is the session that will shift your perspective.

Seats are limited. Register now and witness the moment SoC integration becomes as simple as having a conversation.

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