TSMC and Cadence Strengthen Partnership to Enable Next-Generation AI and HPC Silicon

TSMC continues to reinforce its leadership in advanced semiconductor manufacturing through its deepening collaboration with Cadence Design Systems. The expanded partnership focuses on enabling next-generation artificial intelligence and high-performance computing innovations by aligning advanced electronic design automation, 3D-IC technologies, and silicon-proven intellectual property with TSMC’s most advanced process nodes and packaging platforms.

At the heart of this collaboration is support for TSMC’s cutting-edge process technologies, including N3, N2, and A16™, which are critical for meeting the escalating performance, power efficiency, and scalability demands of AI workloads. Cadence’s AI-driven design flows have been optimized and validated for these nodes, allowing customers to achieve superior power, performance, and area outcomes while accelerating time to market. These flows leverage machine learning–based optimization to address the growing complexity of advanced-node designs, particularly for large-scale AI accelerators and HPC processors.

TSMC’s roadmap toward even more advanced technologies is further strengthened by joint development efforts with Cadence on future nodes, including the upcoming A14 process. Early EDA flow collaboration and PDK readiness ensure that customers can begin design work sooner, reducing risk and enabling faster adoption of next-generation silicon technologies. This early alignment between foundry and EDA provider is increasingly vital as design margins shrink and integration challenges intensify at advanced nodes.

Beyond transistor scaling, the partnership plays a critical role in advancing TSMC’s 3DFabric® platform, which enables heterogeneous integration through advanced packaging and die stacking. Cadence’s comprehensive 3D-IC solutions support a wide range of TSMC 3DFabric configurations, providing automation for bump connections, multi-chiplet physical implementation, and system-level analysis. AI-driven tools such as Clarity™ 3D Solver and Sigrity™ X enable accurate signal integrity, power integrity,  and thermal analysis, helping designers manage the complexities of large, multi-die systems.

Photonics integration is another area of collaboration, particularly through support for TSMC’s Compact Universal Photonic Engine (COUPE™). By combining Cadence’s Virtuoso® Studio and Celsius™ Thermal Solver with TSMC-developed productivity enhancements, customers can more effectively model thermal and electrical interactions in photonic and electronic systems. This capability is increasingly important for AI and data center applications, where power density and thermal management directly impact system reliability and performance.

A key pillar of the Cadence and TSMC partnership is the availability of design-in-ready, silicon-proven IP on advanced nodes such as TSMC N3P. Leading-edge memory and interface IP, including HBM4, LPDDR6/5X, DDR5 MRDIMM Gen2, PCIe® 7.0, and UCIe™, addresses the growing memory bandwidth and interconnect challenges faced by AI systems. These IP offerings enable customers to scale compute performance efficiently while overcoming bottlenecks associated with data movement and power consumption.

Bottom line: Together with the broader Open Innovation Platform® ecosystem, TSMC and Cadence are streamlining the path from design to silicon. By integrating AI-driven EDA, advanced packaging solutions, and next-generation IP with TSMC’s manufacturing leadership, the partnership empowers customers to deliver faster, more energy-efficient AI and HPC solutions. As AI adoption accelerates globally, this close collaboration positions TSMC at the center of the AI semiconductor super-cycle, enabling innovation across the entire value chain, from process technology to system-level integration.

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