Have We Hit the Power Floor?

As we celebrate the 50[SUP]th[/SUP] anniversary of the publication of Moore’s Law in Electronics Magazine (April 19, 1965), the industry finds itself in an increasingly costly global effort to keep transistor scaling on track. “Is Moore’s Law dead?” is a common question these days.

But practically speaking the doubling of transistor density every 18 months or so has been pushed off the front pages in the past decade by the crucial need to manage power.

Joel Hruska, writing in Extremetech, notes:

“One of the most striking characteristics of current semiconductor research is how completely the search for lower-power devices has subsumed the old clock speed obsession. 0W has become the new 1GHz. Performance, the old God of Computing is now merely an efficient means to achieve the lowest possible minimal power usage.”

In recent years, our industry has made enormous strides in power management, breathing longer battery life into smaller and smaller devices. But we’re starting to hear whispers of a question that echoes the one surrounding Moore’s Law: Are we approaching a power floor?

That’s one reason events like the annual Electronic Design Process Symposium (EDPS)—being held April 23-24—have become so critical to nurturing a thoughtful conversation about the future of low-power design.

“EDPS is a excellent opportunity for engineers to glean insight from industry experts on the latest techniques to design to increasingly stringent power budgets, consider emerging materials, and develop design flows that optimize implementation and verification for low-power systems,” said Arpana Dey, technical marketing director for standards at Cadence who serves as the 2015 EDPS chair.

The two-day event is being held at the Monterey Beach Resort in Monterey, Calif., and it will be day two that will offer a day-long deep dive into the most pressing engineering concerns surrounding low-power design.

Jim Kardach, director of integrated products at high frequency power conversion startup FinSix, will keynote first thing Friday morning on “Low Power Design, Standards and Evolution.” Kardach’s keynote will be followed by a series of presentations on “Low Power Technologies and Ecosystems,” a session chaired by Naresh Sehgal, senior program manager for Intel’s Imaging and Camera Group.

The Friday afternoon keynote features University of California San Diego computer science and engineering professor Andrew Kahng, speaking on “EDA/ESL Low Power Design Trends, ISTR/CAD and Tools.”

The low-power focus wraps up Friday afternoon with a panel session that I’ll moderate featuring Kahng, Kardach, Bernard Murphy from Atrenta, Steve Carlson from Cadence, Parasad Subramaniam from eSilicon , and Pat Sheridan from Synopsys. We’ll explore how much lower we can push power or whether we’ve hit the practical floor, especially for IoT designs.

Day one features a keynote from Tom Dillinger, Oracle CAD technology manager, which examines two of today’s key materials choices: fully-depleted silicon-on-insulator (FD-SOI) versus FinFETs. After Dillinger sets the stage, he’ll moderate a panel on the topic featuring Kelvin Low, senior director of foundry marketing with Samsung; Boris Murmann, associate professor of electrical engineering at Stanford; Marco Brambilla, director of engineering with Synapse Design; and Jamei Schaeffer, product line manager with GlobalFoundries.

The afternoon lineup on day one includes a variety of presentations in two sessions, one focusing on multi-die challenges and applications (chaired by EDA 2 ASIC President Herb Reiter), the second on hybrid virtual platforms (chaired by well-known industry analyst Gary Smith).

Here’s a link to the complete EDPS program and a link to the registration page. I look forward to seeing you there!

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