Is Number of Signoff Corners an Issue?

Semiconductor companies continue to use the traditional corner-based signoff approach that has been developed more than 40+ years ago and has since remained mainly unchanged as an industry paradigm. Initially it had 2 corners, namely Worst Case (WC) and Best Case (BC) with the maximum and minimum cell delay respectively. Note that wire and via delays were negligible. Later, the number of corners increased to 4 and after that it has been growing exponentially, especially during last 10-15 years. Figure below illustrates the spread of timing signoff corners used in different design companies.

Number of timing signoff corners
One can see that the number of corners grows exponentially with increase of variation sources for each new technology node. Some people believe that it is possible to reduce corners, but it may be risky to remove any so-called “redundant” (or dominated, or less important, etc.) corners. For example, {SS-process + Fast-Metal} is needed for the setup check, because a violation may happen in a path where launch and data paths are cell-delay dominated and capture is metal-delay dominated. So, using only {SS-process + Slow-Metal} may lead to missing violations. Some companies also ignore a need for more corners to take into account Aging Degradation (AD), multi-voltage non-correlated or partially correlated domains (supplies), the temperature inversion, other effects (like the NTBI, Hot electron injection, etc.), FinFet, DPT (Double Pattern Technology), LSE (Layout Dependent Effects), etc., which may produce the extreme delays in some intermediate points.

Even with so many corners, there is no guarantee that we do not miss some violations due to non-linearity (like the cell delay vs. voltage) and even a non-monotonic behavior (like the temperature-inversion) for some variation-factors, and because of a non-perfectness of conventional tools and derating methods, and ignoring some physical phenomena like correlations. Also, we will need to add at least two more points for Aging Degradation (AD): the BOL (Begging-Of-Life) and the EOL (End-Of-Life).

Note that one can doubt if we really need to run BOL and EOL at all the PVT corners and is it fair to multiply all corners by 2. The answer is “yes ” and an explanation is similar to already used for some other variation-factors—most corners may not need to be run for BOL and EOL for typical paths, but there may be special not typical path structures (with cell- or net-delay dominations in different sub-paths) that need not “typical” age model. Let’s consider one example for hold check. A common mistake: There is no need for using SS library & EOL model, because all cell delays become slower. In reality, for some rare path structures, SS & EOL model is needed, because a violation may occur in a path where the launch and data paths are metal-delay dominated and the capture is cell-delay dominated.

Actually, even more corners may be needed because there is a need to add vias corners (or via RC-models) that are similar to the current wire RC models. Vias delays have become significant and are not correlated with RC-wire models. Example: the worst-case situation (corresponding to the minimum setup slack) is when the RC-worst model is used for wires and the RC-best model is used for vias. The capture path has big via delays with almost no wire delays; and cell delays are irrelevant here. Adding via models will increase the corner number by 4-5x.

Using so many PVT/RC/Via corners (>1000) may be not acceptable from the design time and costs considerations. Also, the number of signoff scenarios is a product of corners and modes (functional, test, etc.) and may become too big to be handled by the IC Compiler (ICC) or PrimeTime (PT) or other similar tools. Additionally, designers need to perform 10-30 ECO iterations for all those scenarios to close timing. The runtime has become a serious issue and may be a work-stop for emerging technologies.

Thus, the question is: Is the corner-based signoff and corner number becoming a serious problem?

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