This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.
The webinar begins by highlighting the critical role of mixed-signal chips in modern applications, then explores the various ECO needs that arise when these chips are part of complex system environments combining diverse analog measurement protocols and digital communication methods. The discussion then focuses on the technical challenges faced by design teams and the solutions provided by Easy-Logic. This segment takes center stage in the webinar, emphasizing the importance of efficient and effective ECO processes in overcoming these challenges within mixed-signal ASIC design.
Mixed-signal ASIC applications
Mixed-signal ASICs are essential in systems that need to process real-world analog signals and perform digital computation or control. These designs are crucial for a wide range of applications, including:
- Smartphones and tablets: Many mixed-signal ASICs, such as power management chips and LCD drivers, are used
- Medical devices: Examples include biosensors and other medical electronics.
- Automotive electronics: These ASICs are used in sensors (image, radar, temperature, etc.) and control units.
- Industrial automation: Mixed-signal ASICs play a role in various motion control applications.
- IoT devices: These designs are integral to the functionality of IoT devices.
Mixed-signal ASICs typically include a combination of analog blocks and digital blocks, and interface circuits for communication protocols like USB, SPI, and I2C.
What causes the high number of functional ECO requests?
Mixed-signal ASICs drive the rapid evolution of everyday applications. While analog circuitry dominates these designs, the digital components introduce a unique set of complex ECO challenges.
The webinar discussion highlights several technical challenges, including:
- Short project cycle (i.e., 6 months per chip) and tight ECO windows
- Multiple successive ECO operations on the same digital block
- RTL design with ECOs performed manually
- ECOs in mixed-level designs that combine both RTL and netlist
- Frequent changes to analog circuitry affect input timing to the digital block
- Customer system specifications require modifications to peripheral blocks
- Scan chain repairs required when the ECO operation disrupts the chain
- ECO logic modifications with limited spare resources available
- ECO requests requested after the test chip release
Easy-Logic’s Proven Expertise
Mixed-signal applications demand tailored ECO solutions—not a traditional one-size-fits-all approach. Easy-Logic provides an innovative approach designed to address these specific challenges.
With over 10 years of experience in solving functional ECO challenges, Easy-Logic offers a comprehensive solution that addresses ECO issues across a wide spectrum of ASIC design. Its technology has been widely deployed across a broad range of customer projects and design segments.
Mixed-signal ASIC design, positioned at one end of the spectrum, represents a diverse range of ECO requirements. This webinar will draw upon Easy-Logic’s extensive ECO expertise and feature the following:
- Practical solutions and methodologies to simplify the ECO process in mixed-signal design
- Specialized tool algorithms developed to significantly optimize logic patch size
- An overview of the underlying technology used to address various ECO challenges
About Easy-Logic Technology
Easy-Logic Technology is a leading provider of cutting-edge functional ECO solutions in the semiconductor industry. With a focus on innovation and customer satisfaction, Easy-Logic Technology delivers advanced tools and technologies that enable its customers to achieve excellence in ASIC design.
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