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EDA
Posted on by Daniel Nenni

TSMC ♥ Mentor (Calibre PERC)

TSMC ♥ Mentor (Calibre PERC)
by Daniel Nenni on 10-29-2013 at 8:00 am
Categories: EDA

As semiconductors become more integrated into our lives reliability is becoming a critical issue. As IP consumes more of our die, IP reliability is becoming a critical issue. As we pack more transistors into a chip, reliability is becoming a critical issue. As we move from 28nm to 20nm to 16nm, reliability is becoming a critical issue. The last time one of my “always on” mobile devices became unreliable I tossed it out my car window on Highway 101. So yes, semiconductor reliability is an issue.

“The goal of TSMC9000 is not only to make IP easy to exchange and re-use within the TSMC Open Innovation Platform® (OIP) environment, but also to ensure dependability, quality and robustness for our customers,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We have done extensive work with Mentor to define the initial reliability checks for TSMC9000, which will help identify design issues that could increase the risk of failures when circuits are operating in the field.”

“Working closely with TSMC, we’ve defined a program that makes advanced reliability checking available to all TSMC OIP IP Alliance partners,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “This means that our mutual customers will be able to incorporate TSMC9000-qualified IP into their designs with a high confidence that those IP blocks will pass full-chip reliability checks at signoff.”

PERC is now integrated into the TSMC 9000 IP program so the hundreds, if not thousands, of IP that flow through TSMC can be verified using focused reliability checks for 28nm, 20nm, and 16nm process nodes. SoC designers can then run PERC at the chip level to revalidate the IP after integration. Given the shrinking design cycles and re-spin costs this is a no brainer. The ROI of a thorough and trusted (repeatable) verification environment is compelling.

To investigate further there are several articles about Calibre PERC on SemiWiki:

Mentor also has a nice Calibre PERC page HERE with white papers, webinars, and videos including this one:

Calibre® PERC[SUP]™[/SUP],Mentor Graphics’ newest reliability verification solution is designed to address your advanced circuit verification needs for electrostatic discharge (ESD), electrical overstress (EOS), signals crossing multiple power domains, advanced ERC and other reliability concerns.

More Articles by Daniel Nenni…..

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