As they have done for the last few years, Atrenta held its fifth annual user group meeting at the Shin Yokohama Kokusai Hotel on September 13. The attendees are a mixture of customers and other interested members of the semiconductor supply chain. There were nearly 90 people there representing 48 different companies in Japan.
The trick for a good user group meeting is to get customers to speak about their actual experience. Nobody wants to spend all day listening to presentations by marketing people. Atrenta seems to have managed to get plenty of representatives of the big Japanese semiconductor companies to present their experiences and so they ended up with a full agenda of detailed technical presentations.
This is what was presented. You can click on any presentation to get more details from the Atrenta website.
- Fujitsu Use of SpyGlass Constraints: How Fujitsu Semiconductor Limited deals with critical timing constraint issues
- Improving FPGA Verification at Hitachi: Use of SpyGlass CDC and Lint by Hitachi Information & Telecommunication Engineering, Ltd. to enhance their FPGA design flow
- MegaChips Uses of SpyGlass Constraints and SpyGlass TXV: MegaChips’ use of SpyGlass Constraints and SpyGlass TXV to create high quality SDC for 3rd party IPs
- Renesas Use of BugScope: Renesas Electronics Corporation using new techniques to confirm the quality of the verification environment for large-scale LSI development
- SpyGlass Physical Use at Hitachi: How Hitachi Storage Development reduced debug iterations and ultimately their design schedule by integrating SpyGlass Physical into their design flow
- SpyGlass Platform Adoption at Denso: The results achieved at the semiconductor circuit R&D department of the Electronics Device Business Unit of Denso by adopting the SpyGlass platform
One interesting fact. Based on a survey conducted at the end of the meeting, over 60% of the attendees showed interest in learning more about BugScope that Atrenta acquired last year when they bought NextOp. Bugscope is a tool that helps generate assertions automatically for assertion-based verification. This is very time-consuming and error-prone to do by hand. As a rule of thumb, you want one assertion for very 10 to 100 lines of RTL but each assertion takes hours to create and debug, so for a sizeable piece of RTL this is a huge undertaking without using Bugscope. Another problem that Bugscope helps with is ensuring that assertion coverage is complete, another task that is notoriously hard to do well manually.
The next Atrenta event coming up in Japan is EDSFair 2013 in the Pacifico Yokohama on Nov 20-23 where Atrenta will have a booth. More details on the EDSFair are herein English and here in Japanese.
Share this post via:
Podcast EP267: The Broad Impact Weebit Nano’s ReRAM is having with Coby Hanoch