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Siemens EDA
Posted on by Daniel Payne

View from the top: Michael Buehler-Garcia

View from the top: Michael Buehler-Garcia
by Daniel Payne on 05-15-2012 at 10:30 am
Categories: EDA, Siemens EDA

Yesterday I met with Michael Buehler-Garcia, Director of Marketing at Mentor Graphics for Calibre in Wilsonville, Oregon to get an update on what’s coming up at DAC, the premier conference and trade show for our industry.



Q: What should we expect from Mentor at DAC in 2012?
A: Mostly you will hear about use-model adoption announcements at 28nm and smaller nodes.

Q: What are the benefits of attending DAC for Mentor customers?
A: One benefit are the three way customer meetings (Foundry, Customer, Mentor – all live) because collaboration is key to IC design. Another benefit are the panel sessions where we have no slides, instead it is spontaneous conversations with plenty of time for Q&A from the audience.

Q: What is Mentor talking about with GLOBALFOUNDRIES?
A: We have three technical seminars with GLOBALFOUNDRIES at DAC:

Q: I’ve been hearing about Double Pattern Technology (DPT) and coloring. Does Mentor have patents in this area?
A: Yes, Mentor has some patents applied for with DPT technology. I can talk more about it when the patents are issued.

Q: How complex is DPT?
A: The ISDA (International Semiconductor Development Alliance) has 6 flavors of DPT usage, so it’s more complex at 20nm than design was at 28nm.

Q: What are the key issues with 20nm design?
A: I would say that at 20nm fill and reliability are key issues that must be dealt with.

Q: How ready is the ecosystem for 20nm?
A: For 20nm design the EDA tools are ready now, so you can certainly get started. You need a technology like SmartFill now. PERC will help your reliability (ESD, latch up, analog). Foundries are supplying PERC decks for 28nm and 20nm. At 28nm PERC is recommend, then at 20nm it becomes required.

Q: For 28nm designs can a customer get a 2nd source?
A: At 28nm the Gate first and Gate last approaches are quite different so migrating becomes a big deal, so it’s not so easy to port your design to a new 28nm foundry.

Q: What is new with PERC these days?
A: With PERC we are seeing an increase in designs at older nodes (180nm, 130nm) where designers are squeezing more efficiency out of 180nm now for mature processes.

Q: What is happening with silicon photonics?
A: Optical DRC will be an interesting challenge because the layout is all curved, so you have to take an equation-based approach. Light waveguides can be built OK at 130nm nodes however the resolution required is at 20nm dimensions.

Summary
Stay tuned for specific announcements in the next two weeks which mention Mentor Graphics, Foundries and customers. Visit Mentor’s site to find out all the events, panels and papers planned for DAC in San Francisco.

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