The second annual Chiplet Summit is coming up and if it is anything like the first one it will not disappoint. Chiplets are a disruptive semiconductor technology that are already being used by the top semiconductor companies like Intel, Nvidia, AMD and others. These companies design their own chiplets so they are blazing the trail for us all.
The next phase of adoption will be commercial chiplets designed by outside sources (IP and ASIC companies) for all to use. Some say the chiplet market could quickly reach $6B and I definitely see that happening. The opportunity for IP and ASIC companies to sell die is just the start. I see a huge upside here, absolutely!
The Chiplet Summit is February 6-8th at my favorite location the Santa Clara Convention Center. The introduction and the keynotes have been posted:
2024 will be a growth year – especially for generative AI and chiplets! Start it off right by meeting with the leading chiplet executives and technologists at the 2nd annual Chiplet Summit. You will hear the latest ideas and breakthroughs, see the new products, learn about generative AI acceleration, and exchange ideas with the industry’s innovators.
We have a new venue with lots of room for conversations, meetings, demonstrations, and posters. Please join us for pre-conference tutorials (including new ones on working with foundries and AI in chiplet design), a superpanel on accelerating generative AI applications, our popular “Chat with the Experts” event, presentations, and exhibits.
Chiplet Summit is the place where the entire ecosystem meets to share ideas across disciplines and keep the chiplet industry moving ahead. Please join us at this must-attend event!
You will hear about industry trends at keynotes from Applied Materials, Synopsys, Micron, Alphawave Semi, Hyperion Technologies, and the Open Compute Project:
Enabling an Open Chiplet Ecosystem at the Package Level
Brian Rea, UCIe™ Consortium
About UCIe™ Consortium: The UCIe Consortium is an industry consortium dedicated to advancing UCIe™ (Universal Chiplet Interconnect Express™) technology, an open industry standard that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. UCIe Consortium is led by key industry leaders Advanced Semiconductor Engineering, Inc. (ASE), Alibaba, AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, NVIDIA, Qualcomm Incorporated, Samsung Electronics, and Taiwan Semiconductor Manufacturing Company. For more information, visit www.UCIexpress.org.
Multi-Die Systems Set the Stage for Innovation
Abhijeet Chakraborty, VP Engineering, Synopsys
Abstract: So far, the only design teams able to handle multi-die systems are bleeding-edge ones accustomed to breaking new ground with every step. Now the ecosystem is providing the tools, IP, standards, connectivity, and manufacturing needed to allow many more teams to switch to this new approach. Multi-die systems are now the mainstream and open up innovation in AI, security, transaction systems, virtual reality, and other areas. They continue the trend established by Moore’s Law to provide more compute power, more memory and storage, and faster I/O in less space and at lower cost.
Creating the Connectivity Required for AI Everywhere
Tony Chan Carusone, CTO, Alphawave Semi
Abstract: All major semiconductor companies now use chiplets for developing devices at leading-edge nodes. This approach requires a die-to-die interface within packages to provide very fast communications. Such an interface is particularly important for AI applications which are springing up everywhere, including both large systems and on the edge. AI requires high throughput, low latency, low energy consumption, and the ability to manage large data sets. The interface must handle needs ranging from enormous clusters requiring optical interconnects to portable, wearable, mobile, and remote systems that are extremely power-limited. It must also work with platforms such as the widely recognized ChatGPT and others that are on the horizon. The right interface with the right ecosystem is critical for the new world of AI everywhere.
New Packaging Technology Accelerates Major Compute Tasks
Sam Salama, Hyperion Technologies
Abstract: Many rapidly emerging compute applications (especially generative AI) need vast computing power and memory capacity. A new 3D packaging technology (QCIA) offers a highly economical solution. It allows larger packages, much higher power dissipation (up to 1000 watts per package), and substrates that exceed 100 mm by 100 mm (beyond the limitations of silicon interposers and without the warpage issues). For example, a single package could hold compute and SRAM devices plus many high- bandwidth memory (HBM) stacks for AI acceleration. Even more should be possible soon as research into new technologies employing < 1-micrometer line/space redistribution layers and panel-processing technologies for bigger packages continues. The development of materials for systems with even higher power dissipation is also ongoing. The QCIA technology can both help meet thermal challenges and deliver fine-pitch connections. It can provide some of the smaller-better-cheaper progress that Moore’s Law can no longer offer.
Creating a Vibrant Open Chiplet Economy
Bapi Vinnakota, Open Compute Project
Abstract: Chiplets have arrived as the way to design very large chips at leading-edge nodes. But how can we take full advantage of the drop-in approach they offer, allowing designers to easily include existing designs at older nodes, IP, and chiplets from outside sources? The OCP believes that an open chiplet economy is the way to go. It will serve the needs of chiplet creators, ASIC designers, and those providing support such as design tools, test facilities, and professional services. Such an economy requires standards, tools, and best practices. The OCP is already pursuing projects that standardize design models, help establish 3rd party testing, improve supply chain methods, define best practices for assembly, and create a standard high- performance, low-power die-to-die interface. The open chiplet economy will benefit large and small organizations alike, and will create huge opportunities for economic growth worldwide.
Many of the Chiplet Summit exhibitors are on SemiWiki so I will definitely be there. 2024 will be a big semiconductor growth year and that will include conference attendance, my opinion.