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There are a large number of challenges at 20nm that didn’t exist at 45nm or even 32nm.
The biggest issues are in the lithography area. Until now it has been possible to make a reticle using advanced reticle enhacement technology (RET) decoration and have it print. Amazing when you think that at 45nm we are making 45nm features… Read More
I have talked quite a bit over the last few years about how the trend towards small consumer devices with very fast ramp times. For example, pretty much any time Apple introduces a new product line (iPod, iPhone, iPad…) it becomes the fastest growing market in history. This has major implications for semiconductor design … Read More
Design constraints, which express higher level design intent, are one of the pieces of ancillary data that are critical to the success or failure of a custom (in fact any) design. Design constraints aren’t usually contained within layout files or library information, but without these critical data, designs may not meet specifications.… Read More
When you think of Indian music you might think of ragas for the sitar. But when you think of Indian MUSIC, that is the Magma user group meeting (Magma Users Summit for Integrated Circuits) coming up on September 7th in Bangalore (note: the date has changed from when it was originally announced). It is at Vivanta by Taj on M G Road.
There… Read More
Jen Hsun Huang, the CEO of nVidia, has a phrase he often repeats to his employees: “We are 30 days from going out of business.” With product cycles as short as 6 months, the troops are on a constant march to revenue. The earnings conference call on August 11th highlighted two critical pieces of information. First, is the success that… Read More
It is no secret that SoC designs continue to increase in complexity and time-to-market windows are shrinking. While there is room for debate on just how big a fraction of SoC design effort goes on verification, there is no debating that it is a large part of the total. Simulation is increasingly too slow, especially when software … Read More
At DAC SpringSoft had a couple of video games set up, one about functional verification and one about, surprise, physical layout. But you didn’t need to go to DAC, you can play them now:
Liberate your Layout
…when Synopsys is getting the lion’s share in Interface IP. In Q2 2010, there was two major acquisitions in EDA world: Synopsys has bought Virage Logic (for more than $300M) when Cadence bought Denali for an equivalent amount. Synopsys bought a 100% IP focused company, when Cadence bought a strongly VIP focused company. Does it … Read More
Hard to believe EDA360, the Cadence Blueprint toBattle ‘Profitability Gap’; Counters Semiconductor Industry’s Greatest Threat!, is DEAD at the ripe old age of one. As you may have already read John Bruggeman left Cadence after the company conference call last week. The formal announcement should go out on Monday after the SEC… Read More
During the next 6 months or so, SpringSoft will be running a dozen community conferences. These are open not just to users but to anyone interested in SpringSoft’s technology.
There will be 3 conferences in US in October in Irvine, Austin and San Jose. For more details as they become available check here. There will be three… Read More
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