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On Monday morning at IEDM, Sri Samavedam of Imec opened the technical program with a plenary talk entitled “Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips”. I am not generally a fan of plenary talks, I think the presenters often try to cover too much in their talks and end up not providing enough detail to be… Read More
Probably the least appreciated and most critical thing I spend my time on when driving custom silicon projects is setting up the entire framework to get everyone talking and in rhythm with each other. Only supplier selection is more critical to the project’s success than this.
All system custom silicon projects where the… Read More
System-level expertise, once the domain a few architecture specialists, is now shouldering its way everywhere into chip design and verification. In virtual modeling together with OS and application software certainly. That now couples into mixed-level system-verification, using different levels of abstraction for different… Read More
In my prior post on NetApp, I discussed how the company’s FlexCache technology can keep distributed design teams in sync. Coordination and collaboration are critical elements of any complex design project. The ability to deliver results quickly while managing the massive amounts of data is also a critical element of success.… Read More
US BIS confirms our prediction of “blacklisting” SMIC
SMIC embargoed from 10NM or better technology
Likely related to ASML pressure & WH scorched earth
We had received a lot of feedback on our Nov 30th note regarding blacklisting of SMIC suggesting that we were wrong and the only thing blacklisted… Read More
A few weeks ago I wrote about an upcoming event Silicon Catalyst was hosting, the Semiconductor Industry Forum – A View to the Future. I mentioned a high-profile group of presenters: Don Clark, Contributing Journalist, New York Times as moderator; Mark Edelstone, Chairman of Global Semiconductor Investment Banking, Morgan… Read More
Normally I would post this Accellera update during DVCon US but, no surprise, this year is weird. Particularly in conferences going virtual. The last DVCon was in early March of this year, right on the cusp of the shutdown. I was there in person, as was Lu Dai (Chairman of Accellera). Both Synopsys and Cadence had dropped out, citing… Read More
I used to be part of the custom silicon management team at Apple. I’ve seen how great a challenge it is to pull off a custom silicon strategy within a one year product cycle. Apple is the perfect example of this custom silicon model since they develop the best mobile processors in the world for their products. Which also includes other… Read More
Earlier this year I wrote about Silicon Catalyst and a potent new addition to their In-Kind and Strategic Partner Programs, Arm. Fast-forward to today and there are real results to report. As I mentioned in the prior post, Silicon Catalyst provides a unique incubator environment which includes deeply discounted technology … Read More
As semiconductor designs for many popular products move into smaller process nodes, the need for effective and rapid design closure is increasing. The SOCs used for many consumer and industrial applications are moving to FinFET nodes from 16 to 7nm and with that comes greater challenges in obtaining design closure. einfochips,… Read More
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