At DVCon U.S. 2026, Accellera Systems Initiative reinforces its central role in shaping the future of electronic design and verification through a focused program of workshops, tutorials, and community engagement. As system complexity continues to rise across AI, automotive, HPC, and communications markets, the need for… Read More
Podcast EP330: An Overview of DVCon U.S. 2026 with Xiaolin Chen
Daniel is joined by Xiaolin Chen, Senior Director of Technical Product Management for Formal Solutions at Synopsys. She has over 20 years of experience applying formal technology in verification and partnering with customers to identify opportunities where formal methods are best suited to solve complex verification challenges.… Read More
Boosting SoC Design Productivity with IP-XACT
IP-XACT, defined by IEEE 1685, is a standard that pulls together IP packaging, integration, and reuse. For anyone building modern SoCs (Systems on Chip), IP-XACT isn’t just another XML schema: it is a productivity multiplier and a risk-reduction tool that brings order to your electronic system design.
What is IP-XACT?
IP-XACT… Read More
Podcast EP310: On Overview of the Upcoming DVCon Europe Conference and Exhibition with Dr. Mark Burton
Daniel is joined by Dr. Mark Burton, the General Chair for this year’s DVCon Europe. DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits.
Mark shares his long history of involvement in DVCon with Dan. He … Read More
Insider Opinions on AI in EDA. Accellera Panel at DAC
In AI it is easy to be distracted by hype and miss the real advances in technology and adoption that are making a difference today. Accellera hosted a panel at DAC on just this topic, moderated by Daniel Nenni (Mr. SemiWiki). Panelists were: Chuck Alpert, Cadence’s AI Fellow driving cross-functional Agentic AI solutions throughout… Read More
Accellera at DVCon 2025 Updates and Behavioral Coverage
As usual I check in on Accellera activities each year at DVCon. Lu Dai (chair) gave an opening talk at the Accellera lunch, with contributions from other speakers on a few topics. In the afternoon I heard an update on PSS 3.0. What follows is a quick summary with my own musings on behavioral coverage.
Notable non-PSS topics
Karsten … Read More
Accellera 2024 End of Year Update
From my viewpoint, standards organizations in semiconductor design always looked like they were “sharpening the saw”: further polishing/refining what we already have but not often pushing on frontiers. Very necessary of course to stabilize and get common agreement in standards but equally always seeming to be behind the innovation… Read More
SystemC Update 2024
SystemC version 1.0 came out in 2000 as a C++ class library for system-level modeling and simulation, and on SemiWiki.com there are some 497 references to the language. I wanted to provide an update in this blog so that engineering teams can become more efficient in using SystemC on their SoC projects, saving time and improving product… Read More
Notes from DVCon Europe 2024
The 2024 DVCon (Design and Verification) Europe conference took place on October 15 and 16, in its traditional location at the Holiday Inn Munich City Centre. Artificial intelligence and software were prominent topics, along with the traditional DVCon topics like virtual platforms, RTL verification, and validation.
Keynotes:
… Read MoreAccellera and PSS 3.0 at #61DAC
Accellera invited me to attend their #61DAC panel discussion about the new Portable Stimulus Standard (PSS) v3.0, and the formal press release was also just announced. The big idea with PSS is to enable seamless reuse of stimulus across simulation, emulation and post-silicon debug and prototyping.
Tom Fitzpatrick from Siemens… Read More

