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Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage

Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
by Eric Esteve on 01-17-2013 at 10:52 am

We all know the concept of “one stop shop”, becoming popular in the Design IP market. The topic we will address today is NOT the “one stop shop”, even if it looks similar, but rather that we could call “consistent design flow”.

What does that means? Simply that, if your SoC design is integrating a DDRn (LPDDR2, DDR3 or even DDR4, let’s… Read More


Subsystem IP, myth or reality?

Subsystem IP, myth or reality?
by Eric Esteve on 12-07-2012 at 5:00 am

I have participated to a panel during IP-SoC, I must say that “Subsystem IP, myth or Reality” was a great moment. The panel was a mix of mid-size IP vendor (CAST, Sonics), one large EDA (Martin Lund from Cadence), Semiwiki blogger and one large IDM (Peter Hirt from STM) who has very well represented the customer side. And, to make the… Read More


Give me a pair of wires, I’ll give you Ethernet in cars

Give me a pair of wires, I’ll give you Ethernet in cars
by Don Dingee on 11-27-2012 at 10:00 pm

A very astute gentleman said to me a few years ago that he’d seen a lot of networking technology come and go – Token Ring, FDDI, Fibre Channel, InfiniBand – but the only one that held up over time was Ethernet.… Read More


Cadence sets the Global Standards in VIP for AMBA based SoC

Cadence sets the Global Standards in VIP for AMBA based SoC
by Eric Esteve on 11-12-2012 at 11:48 am

We have shown in Semiwiki how strong Cadence position was in Verification IP (VIP) in a previous post focusing on Interface standards like SuperSpeed USB or PCI Express. But IP based functions are used everywhere in a SoC, not only to interface with the external world, and need to be verified, as well, like for AMBA based functions.… Read More


New MIPI protocols: Unipro, LLI and CSI3 over MPHY.

New MIPI protocols: Unipro, LLI and CSI3 over MPHY.
by Eric Esteve on 10-04-2012 at 8:10 am

New MIPI protocols: Unipro, LLI and CSI3 over MPHY.

Gabriele ZARRI, Moshik RUBIN, Cadence
Sophia Antipolis, France SAME 2012 Conference – October 2 & 3, 2012 2

Abstract:

With more than 50% of the world‟s population using cellular phones and the growing number of devices that go mobile, from game consoles and media player… Read More


SAME 2012 Conference on October 2-3 in Sophia is coming soon!

SAME 2012 Conference on October 2-3 in Sophia is coming soon!
by Eric Esteve on 09-24-2012 at 11:01 am

This is the 15[SUP]th[/SUP] anniversary for the SAME Conference, dedicated to innovation on Microelectronics. Sophia-Antipolis is not only close to Mediterranean sea, but also at the heart of Telecom valley in south of France, with Texas Instruments design center dedicated to Application Processor design (OMAP), Cadence… Read More


Cadence September News: strong IP and VIP focus

Cadence September News: strong IP and VIP focus
by Eric Esteve on 09-14-2012 at 4:25 am

There are three articles on the front page, in the September release of Cadence newsletter, all of them are dedicated to either IP (DDR4), VIP (NVM express VIP being used at Samsung) or Martin Lund. You can read Martin’s interview here and/or take a look at what I write about him this summer. This strong focus on IP, and in fact on Interface… Read More


Is DDR4 a bridge too far?

Is DDR4 a bridge too far?
by Don Dingee on 09-11-2012 at 8:30 pm

We’ve gone through two decades where the PC market made the rules for technology. The industry faces a question now: Can a new technology go mainstream without the PC?

By now, you’ve certainly read the news from Cadence on their DDR4 IP for TSMC 28nm. They are claiming a PHY implementation that exceeds the data rates specified for … Read More


Shorter, better and easier PCIe and NVM Express Verification flow with advanced technologies

Shorter, better and easier PCIe and NVM Express Verification flow with advanced technologies
by Eric Esteve on 07-19-2012 at 8:05 pm

We have talked about Cadence subsystem IP strategy, illustrated by NVM Express subsystem IP, in a previous blog. What we said was that “A subsystem IP based approach will also speed up the software development and validation phase: if the IP provider is able to propose the right tools, like the associated Verification IP (VIP), … Read More


Cadence’s NVM Express: fruit from subsystem IP based strategy

Cadence’s NVM Express: fruit from subsystem IP based strategy
by Eric Esteve on 07-02-2012 at 11:24 am

If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application… Read More