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Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.

Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.
by Eric Esteve on 01-12-2012 at 9:45 am

I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their… Read More


ARM TechCon 2011 Trip Report and Sailing Semiconductors!

ARM TechCon 2011 Trip Report and Sailing Semiconductors!
by Daniel Nenni on 10-26-2011 at 9:37 pm

This was my first ARM TechCon, they cordially invited me as media, but it certainly was not what I expected. Making matters worse, I had literally just flown in from a very long weekend sailing in Mexico which was much more interesting and certainly made me much less tolerant of sales and marketing nonsense. My Uncle Jim lives on a sailboat… Read More


Cadence VIP Enables Users to be First-to-Market with Mobile Devices Leveraging Latest MIPI, LPDDR3 and USB 3.0 OTG Standards

Cadence VIP Enables Users to be First-to-Market with Mobile Devices Leveraging Latest MIPI, LPDDR3 and USB 3.0 OTG Standards
by Eric Esteve on 09-27-2011 at 1:56 am

The mobile devices market is simply exploding, with smartphones shipmentgoing up to the sky, tabletsemerging so fast that some people think it will replace PC (but this is still to be confirmed…). This lead mobile SoC designs to integrate increasingly more features, to support customer needs for more computing power and sophisticated… Read More


Cadence Verification IP Technical Seminar!

Cadence Verification IP Technical Seminar!
by Daniel Nenni on 08-22-2011 at 11:43 am

According to trusted sources it costs upwards of $50M to design a 40nm SoC down to the GDS. Semiconductor IP is a fast growing part of that equation and functional verification of that IP is critical. Hardware complexity growth continues to follow Moore’s Law but verification complexity is even more challenging. In fact, IP verification… Read More