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Cadence
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Cadence IP Strategy 2012

Cadence IP Strategy 2012
by Daniel Nenni on 06-17-2012 at 7:00 pm
Categories: Cadence, IP

As I mentioned in a previous blog Cadence Update 2012, Martin Lund is now in charge of the Cadence IP strategy. Martin read my first blog and wanted to exchange IP strategies so we met at DAC 2012 for a chat. Not only did Martin connect with me on LinkedIn, he also joined the SemiWiki LinkedIn group, which now has 4,000+ members. So yes,… Read More

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Semiconductor Ecosystem Keynotes: ARM 2012

Semiconductor Ecosystem Keynotes: ARM 2012
by Daniel Nenni on 05-17-2012 at 5:00 pm
Categories: Arm, Cadence, EDA, ESD Alliance, GlobalFoundries, IP, Semiconductor Services, Synopsys, TSMC
2 Comments

Yesterday’s SEMICO IP Ecosystem Conference was well worth the time. Everybody was there: ARM, Synopsys, Cadence, Mentor Graphics, GlobalFoundries, TSMC, MIPS, Tensilica, AMD, Atrenta, Sonics, and Tabula, everybody except Intel of course. What do Intel and I have in common? We don’t play well with others…

First up was… Read More

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Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support

Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
by Eric Esteve on 04-11-2012 at 10:19 am
Categories: Cadence, IP

The press release about ONFI 3.0 support was launched by Cadence at the beginning of this year. It was a good illustration of Denali, then Cadence, long term commitment to Nand Flash Controller IP support. The ONFI 3 specification simplifies the design of high-performance computing platforms, such as solid state drives and enterprise… Read More

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According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012

According with Cadence, PCI Express gen-3, to be the PCIe solution for the mainstream market as soon as in 2012
by Eric Esteve on 03-21-2012 at 9:10 am
Categories: Cadence, IP

The launch from Cadence of the PCI Express 3.0 Controller IP was officially done about one year ago, and demonstrated at the June 2011 PCI-SIG Developer’s Conference, where Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller… Read More

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Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.

Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let’s have a look at Cadence’s strategy.
by Eric Esteve on 01-12-2012 at 9:45 am
Categories: Cadence, IP

I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their… Read More

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ARM TechCon 2011 Trip Report and Sailing Semiconductors!

ARM TechCon 2011 Trip Report and Sailing Semiconductors!
by Daniel Nenni on 10-26-2011 at 9:37 pm
Categories: Arm, Cadence, IP, Siemens EDA, TSMC

This was my first ARM TechCon, they cordially invited me as media, but it certainly was not what I expected. Making matters worse, I had literally just flown in from a very long weekend sailing in Mexico which was much more interesting and certainly made me much less tolerant of sales and marketing nonsense. My Uncle Jim lives on a sailboat… Read More

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Cadence VIP Enables Users to be First-to-Market with Mobile Devices Leveraging Latest MIPI, LPDDR3 and USB 3.0 OTG Standards

Cadence VIP Enables Users to be First-to-Market with Mobile Devices Leveraging Latest MIPI, LPDDR3 and USB 3.0 OTG Standards
by Eric Esteve on 09-27-2011 at 1:56 am
Categories: Cadence, IP

The mobile devices market is simply exploding, with smartphones shipmentgoing up to the sky, tabletsemerging so fast that some people think it will replace PC (but this is still to be confirmed…). This lead mobile SoC designs to integrate increasingly more features, to support customer needs for more computing power and sophisticated… Read More

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Cadence Verification IP Technical Seminar!

Cadence Verification IP Technical Seminar!
by Daniel Nenni on 08-22-2011 at 11:43 am
Categories: Cadence, IP

According to trusted sources it costs upwards of $50M to design a 40nm SoC down to the GDS. Semiconductor IP is a fast growing part of that equation and functional verification of that IP is critical. Hardware complexity growth continues to follow Moore’s Law but verification complexity is even more challenging. In fact, IP verification… Read More