Verification has long been the most time-consuming and often resource-intensive part of chip development. Building out the infrastructure to tackle verification can be a costly endeavor, however. Emerging and even well-established semiconductor companies must weigh the Cost-of-Results (COR) against Time-to-Results
WEBINAR: Unlock your Chips’ Full Data Transfer Potential with Interlaken
Way back in the early 2000s when XAUI was falling short on link flexibility a search for an alternative chip-to-chip data transfer interface with SPI like features lead Cisco Systems and Cortina System to put forward the proposal for the Interlaken standard. The new standard married the best of XAUI’s serialized data and SPI’s … Read More
WEBINAR The Rise of the SmartNIC
A recent live discussion between experts Scott Schweitzer, Director of SmartNIC Product Planning with Achronix, and Jon Sreekanth, CTO of Accolade Technology, looked at the idea behind the rise of the SmartNIC and ran an “ask us anything” session fielding audience questions about the technology and its use cases.
Three phases
… Read MoreSamtec is Fueling the AI Revolution
It’s all around us. The pervasive use of AI is changing our world. From planetary analysis of weather patterns to monitoring your vital statistics to assess health, it seems as though smart everything is everywhere. Much has been written about the profound impact AI is having on our lives and society. Everyone seems to agree that… Read More
Webinar: Semifore Offers Three Perspectives on System Design Challenges
The exponential increase in design complexity is a popular topic these days. In fact, it’s been a topic of discussion for a very long time. The explosion of chip and system design complexity over the past ten years has become legendary and haunts many of us daily. A lot of the complexity we face has to do with coordinating across an ever-increasing… Read More
Why China hates CHIPS
The CHIPS and Science Act has its fair share of critics, with detractors calling it corporate welfare for “losers” like Intel, or lacking guardrails to prevent companies making legacy chips in China.
One of the most vocal opponents of the act has been China’s communist-ruled government.
WEBINAR: Intel Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are
2022 Semiconductor Supercycle and 2023 Crash Scenario
Charles Shi, semiconductor analyst at Needham & Company, an US-based investment bank and asset management firm, hosted an expert call on semiconductor cycles with Malcolm Penn, Founder and CEO of Future Horizons on 18 August 2022, with over 100 financial analysts in attendance. The following bulletin is a summary of the… Read More
Enhanced X-NAND flash memory architecture promises faster, denser memories
Although the high-performance X-NAND memory cell and architecture were first introduced in 2020 by Neo Semiconductor, designers at Neo haven’t rested on that accomplishment and recently updated the cell and the architecture in a second-generation implementation to achieve 20X the performance of conventional quad-level-cell… Read More
Getting Ahead with Semiconductor Manufacturing Equipment and Related Plasma Reactors
Advanced semiconductor fabrication technology is what makes it possible to pack more and more transistors into a sq.mm of a wafer. The rapidly increasing demand for advanced-process-based chips has created huge market opportunities for semiconductor manufacturing equipment vendors. According to SEMI, worldwide sales … Read More


Semidynamics Unveils 3nm AI Inference Silicon and Full-Stack Systems