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14nm 16nm 10nm and 7nm – What we know now

14nm 16nm 10nm and 7nm – What we know now
by Scotten Jones on 04-07-2017 at 7:00 am

Last week Intel held a manufacturing day where they revealed a lot of information about their 10nm process for the first time and information on competitor processes continues to slowly come out as well. I thought it would be useful to summarize what we know now, especially since some of what Intel announced was different than what… Read More


Shootout at 22nm!

Shootout at 22nm!
by Scotten Jones on 04-03-2017 at 4:00 pm

For an industry that drives improvement at an exponential rate it is funny how often something old is new again. Intel went into high volume production on 22nm in 2011, and TSMC and Samsung have both had 20nm technologies in production for several years. And yet, recently we have seen renewed interest in 22nm. GLOBALFOUNDRIES has… Read More


Everything a Designer Wants to Ask About FDSOI

Everything a Designer Wants to Ask About FDSOI
by Adele Hars on 04-01-2017 at 12:00 pm

So you’ve got questions about FD-SOI? For chip designers in Silicon Valley, there’s a great opportunity to get answers from some of the world’s leading design experts. It’s coming up fast: April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. Bear in mind that Read More


Caution: Reset Domains Crossing

Caution: Reset Domains Crossing
by Bernard Murphy on 04-01-2017 at 7:00 am

Because you can never have too much to worry about in verification, reset domain crossings (RDCs) are another hazard lying in wait to derail your design. Which hardly seems fair. We like to think of resets as dependable anchors to get us back on track when all else fails, but it seems their dependability is not absolute, especially… Read More


Analyzing All of those IC Parasitic Extraction Results

Analyzing All of those IC Parasitic Extraction Results
by Daniel Payne on 03-30-2017 at 12:00 pm

Back at DAC in 2011 I first started to hear about this EDA company named edXact that specialized in reducing and analyzing IC parasitic extraction results. So Silvaco acquired edXact and I wanted to get an update on what is new with their EDA tools that help help you to analyze and manage the massive amount of extracted RLC and even K … Read More


SNUG 2017 Keynote: Aart de Geus on EDA Fusion!

SNUG 2017 Keynote: Aart de Geus on EDA Fusion!
by Daniel Nenni on 03-30-2017 at 7:00 am

I spoke with Aart before his SNUG keynote and found him to be very relaxed and upbeat about EDA and our future prospects which reminded me of my first ever (cringe-worthy) blog, “EDA is Dead”. Now, eight years later, we have what Aart calls “EDA Fusion” to thank for the reemergence of EDA as a semiconductor superpower, absolutely.… Read More


When is "off" not really off?

When is "off" not really off?
by Tom Simon on 03-29-2017 at 12:00 pm

With the old fashioned on-off power switch came certainty of power consumption levels. This was fine back in the days before processor controlled appliances and devices. On was on and off was off: full current or no current. With the first personal computers you always had to wait for the boot process to complete before you could … Read More


Who knew designing PLL’s was so complicated?

Who knew designing PLL’s was so complicated?
by Tom Simon on 03-27-2017 at 12:00 pm

Well it comes as no surprise to those that use and design them, that PLL’s are a world unto themselves and very complicated indeed. With PLL’s we are talking about analog designs that rely on ring oscillators or LC tanks. They are needed on legacy nodes, like the ones that IoT chips are based on, and they are crucial for high speed advanced… Read More