Last week GLOBALFOUNDRIES and Mentor Graphics presented at the Tech Design Forum on how they collaborated on a third generation DFM flow. When I reviewed the slides of the presentation it really struck me on how the old thinking in DRC (Design Rule Checking) of Pass/Fail for layout rules had been replaced with a score represented… Read More
I love you, you love me, we’re a happy family…
The CEO panel at the 2nd GTC wasn’t especially enlightening. The theme was that going forward will require cooperation for success and everyone was really ready to cooperate.
The most interesting concept was Aart talking about moving from what he called “scale complexity” aka Moore’s law to what he … Read More
Third Generation DFM Flow: GLOBALFOUNDRIES and Mentor Graphics
Introduction
Mentor Graphics and GLOBALFOUNDRIES have been working together for several generations since the 65nm node on making IC designs yield higher. Michael Buehler-Garcia, director of Calibre Design SolutionsMarketing at Mentor Graphics spoke with me by phone today to explain how they are working with GLOBALFOUNDRIES… Read More
Mentor catapults Calypto
Mentor has transferred its Catapult (high level synthesis) product line, including the people, to Calypto. Terms were not disclosed but apparently it is a non-cash deal. Calypto gets the product line. Mentor gets a big chunk of ownership of Calypto. So maybe the right way to look at this is as a partial acquisition of Calypto.
It … Read More
Aug 25th in Fremont, CA – Hands on Calibre workshop: DRC, LVS, xRC, ERC, DFM
I’ve blogged about the Calibre family of IC design tools before:
Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better… Read More
OPC Model Accuracy and Predictability – Evolution of Lithography Process Models, Part III
Wyatt Earp probably wasn’t thinking of OPC when he said, “Fast is fine, but accuracy is everything,” but I’ll adopt that motto for this discussion of full-chip OPC and post-OPC verification models.
Accuracy is the difference between the calibrated model prediction and the calibration wafer result. Accuracy depends on several… Read More
Best EDA company for work life balance?
What was the first EDA company name that came to your mind after reading that title?
At Forbes magazine they rated both Mentor Graphics and Synopsys in the top 25 best companies for work life balance.
That’s quite an honor for both Mentor and Synopsys so I can say that EDA dominated the list this year.
Here are some of the factors… Read More
August 11th – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC
I’ve blogged about the Calibre family of IC design tools before:
Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better… Read More
Smart Fill Replaces Dummy Fill Approach in a DFM Flow
I met with Jeff Wilson, Product Marketing Manager at Mentor in the Calibre product group to learn more about Smart Fill versus Dummy Fill for DFM flows. Jeff works in the Wilsonville, Oregon office and we first meet at Silicon Compilers back in the 1990’s.
Dummy Fill
This diagram shows an IC layout layer on the left as originally… Read More
Want to learn Mixed-Signal Design and Verification?
Workshops are a great where to learn hands-on about IC design technology. Mentor has a free workshop to introduce you to creating, simulating and verifying mixed-signal (Analog and Digital) designs.
PLL waveforms showing both digital and analog signals.
Dates in Fremont, California
July 26, 2011
September 15, 2011
November… Read More