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Q2FY24TessentAI 800X100
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Design & Verification of Platform-Based, Multi-Core SoCs

Design & Verification of Platform-Based, Multi-Core SoCs
by Daniel Payne on 02-02-2012 at 11:16 am

Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More


The Future of Lithography Process Models

The Future of Lithography Process Models
by Beth Martin on 01-30-2012 at 4:02 pm

Always in motion is the future. ~Yoda

For nearly ten years now, full-chip simulation engines have successfully used process models to perform OPC in production. New full-chip models were regularly introduced as patterning processes evolved to span immersion exposure, bilayer resists, phase shift masking, pixelated illumination… Read More


SemiWiki and Mentor Graphics Seminar Series!

SemiWiki and Mentor Graphics Seminar Series!
by Daniel Nenni on 01-28-2012 at 10:49 am

For the greater good of the semiconductor ecosystem, SemiWiki and Mentor Graphics present SemiWiki Seminars, a free seminar and software demonstration series addressing the latest innovations in IC design. SemiWiki Seminars discuss interesting new challenges and potential solutions aimed at increased circuit density … Read More


Going up…3D IC design tools

Going up…3D IC design tools
by Paul McLellan on 01-23-2012 at 6:41 pm

3D and 2.5D (silicon interposer) designs create new challenges for EDA. Not all of them are in the most obvious areas. Mentor has an interesting presentation on what is required for verification and testing of these types of designs. Obviously it is somewhat Mentor-centric but in laying out the challenges it is pretty much agnostic.… Read More


What is a Hierarchical SPICE Circuit Simulator?

What is a Hierarchical SPICE Circuit Simulator?
by Daniel Payne on 01-19-2012 at 2:56 pm

Hierarchy is used in IC designs at many abstraction levels to help describe a design in a compact format:

  • Mask Data
  • IC Layout
  • Schematic Netlists
  • Gate level netlists
  • RTL netlists

But the question and focus for this blog is, “What is a hierarchical SPICE Circuit Simulator?”… Read More


Advanced Memory Cell Characterization with Calibre xACT 3D

Advanced Memory Cell Characterization with Calibre xACT 3D
by SStalnaker on 01-12-2012 at 7:18 pm

Advanced process technologies for manufacturing computer chips enable more functionality, higher performance, and low power through smaller sizes. Memory bits on a chip are predicted to double every two years to keep up with the demand for increased performance.

To meet these new requirements for performance and power, memory… Read More


EDA Vendors Providing Secure Remote Support for an IC Design Flow

EDA Vendors Providing Secure Remote Support for an IC Design Flow
by Daniel Payne on 01-05-2012 at 5:38 pm

In my last corporate EDA job I had customers in Korea that were evaluating a new circuit simulator and getting strange results. When I asked, “Could you send me your test case?” the reply was always, “No, we cannot let any of our IC design data leave the building because of security concerns.”… Read More


iLVS: Improving LVS Usability at Advanced Nodes

iLVS: Improving LVS Usability at Advanced Nodes
by glforte on 12-13-2011 at 4:54 pm

LVS Challenges at Advanced Nodes

Accurate, comprehensive device recognition, connectivity extraction, netlist generation and, ultimately, circuit comparison becomes more complex with each new process generation. As the number of layers and layer derivations increases the complexity of devices, especially Layout Dependent… Read More


Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes

Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes
by glforte on 12-07-2011 at 3:52 pm

Preventing electrical circuit failure is a growing concern for IC designers today. Certain types of failures such as electrostatic discharge (ESD) events, have well established best practices and design rules that circuit designers should be following. Other issues have emerged more recently, such as how to check circuits… Read More