WP_Term Object
(
    [term_id] => 159
    [name] => Siemens EDA
    [slug] => siemens-eda
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 752
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 752
    [category_description] => 
    [cat_name] => Siemens EDA
    [category_nicename] => siemens-eda
    [category_parent] => 157
    [is_post] => 
)
            
Q2FY24TessentAI 800X100
WP_Term Object
(
    [term_id] => 159
    [name] => Siemens EDA
    [slug] => siemens-eda
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 752
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 752
    [category_description] => 
    [cat_name] => Siemens EDA
    [category_nicename] => siemens-eda
    [category_parent] => 157
    [is_post] => 
)

3D-IC Testing – A 3D perspective to SoC

3D-IC Testing – A 3D perspective to SoC
by Pawan Fangaria on 03-21-2012 at 9:30 am

In my last article I talked about the physical design aspect of 3D-IC. Now looking at its verification aspect, it spans through a wide spectrum of test at hardware as well as software level. The verification challenge goes much beyond that of a SoC which is at a single plane. Even a typical SoC that comprises of a processor core, memory… Read More


Double Patterning and Then The End of Lithography

Double Patterning and Then The End of Lithography
by Paul McLellan on 03-15-2012 at 8:00 am

I went to a couple more sessions at the Common Platform Technology Forum today, on 20nm double patterning and whatever will we do at 14nm. Basically, this is the end of planar transistors and the end of optical lithography. One session was by IBM scientists about process and one by Michael White of Mentor about double patterning. … Read More


Common Platform Technology Forum: Peering into the Future

Common Platform Technology Forum: Peering into the Future
by Paul McLellan on 03-10-2012 at 9:00 am

Next Wednesday is the Common Platform Technology Forum. “Common Platform” is a name that only a committee could have come up with, giving no clue as to what it actually is. As you probably know, there are various process clubs sharing the costs of technology development (TD) and one of them consists of IBM, Samsung and… Read More


Seminar on IC Yield Optimization at DATE on March 14th

Seminar on IC Yield Optimization at DATE on March 14th
by Daniel Payne on 02-22-2012 at 3:59 pm

My first chip design at Intel was a DRAM and we had a 5% yield problem caused by electromigration issues, yes, you can have EM issues even with 6um NMOS technology. We had lots of questions but precious few answers on how to pinpoint and eliminate the source of yield loss. Fortunately, with the next generation of DRAM quickly introduced… Read More


DFM Industry Survey

DFM Industry Survey
by Beth Martin on 02-10-2012 at 1:28 pm

As part of the DFM Conference at the SPIE Advance Lithography symposium, the DFM committee is conducting an informal survey on the current state of Design For Manufacturability in the Semiconductor Industry.

Please take this anonymous 16 question survey to identify critical Design for Manufacturability (DFM) issues facing… Read More


DFM at SPIE Advance Litho show

DFM at SPIE Advance Litho show
by Beth Martin on 02-09-2012 at 6:40 pm

This year’s SPIE Advanced Lithography is loaded with interesting keynotes and sessions. To help me narrow down what to see, I spoke with John Sturtevant. John is co-chair of the Design for Manufacturability through Design-Process Integration conference, and the director for technical marketing for RET products at Mentor Graphics.… Read More


Design & Verification of Platform-Based, Multi-Core SoCs

Design & Verification of Platform-Based, Multi-Core SoCs
by Daniel Payne on 02-02-2012 at 11:16 am

Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More


The Future of Lithography Process Models

The Future of Lithography Process Models
by Beth Martin on 01-30-2012 at 4:02 pm

Always in motion is the future. ~Yoda

For nearly ten years now, full-chip simulation engines have successfully used process models to perform OPC in production. New full-chip models were regularly introduced as patterning processes evolved to span immersion exposure, bilayer resists, phase shift masking, pixelated illumination… Read More


SemiWiki and Mentor Graphics Seminar Series!

SemiWiki and Mentor Graphics Seminar Series!
by Daniel Nenni on 01-28-2012 at 10:49 am

For the greater good of the semiconductor ecosystem, SemiWiki and Mentor Graphics present SemiWiki Seminars, a free seminar and software demonstration series addressing the latest innovations in IC design. SemiWiki Seminars discuss interesting new challenges and potential solutions aimed at increased circuit density … Read More