WP_Term Object
(
    [term_id] => 159
    [name] => Siemens EDA
    [slug] => siemens-eda
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 749
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 749
    [category_description] => 
    [cat_name] => Siemens EDA
    [category_nicename] => siemens-eda
    [category_parent] => 157
    [is_post] => 
)
            
Q2FY24TessentAI 800X100
WP_Term Object
(
    [term_id] => 159
    [name] => Siemens EDA
    [slug] => siemens-eda
    [term_group] => 0
    [term_taxonomy_id] => 159
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 749
    [filter] => raw
    [cat_ID] => 159
    [category_count] => 749
    [category_description] => 
    [cat_name] => Siemens EDA
    [category_nicename] => siemens-eda
    [category_parent] => 157
    [is_post] => 
)

Seminar on IC Yield Optimization at DATE on March 14th

Seminar on IC Yield Optimization at DATE on March 14th
by Daniel Payne on 02-22-2012 at 3:59 pm

My first chip design at Intel was a DRAM and we had a 5% yield problem caused by electromigration issues, yes, you can have EM issues even with 6um NMOS technology. We had lots of questions but precious few answers on how to pinpoint and eliminate the source of yield loss. Fortunately, with the next generation of DRAM quickly introduced… Read More


DFM Industry Survey

DFM Industry Survey
by Beth Martin on 02-10-2012 at 1:28 pm

As part of the DFM Conference at the SPIE Advance Lithography symposium, the DFM committee is conducting an informal survey on the current state of Design For Manufacturability in the Semiconductor Industry.

Please take this anonymous 16 question survey to identify critical Design for Manufacturability (DFM) issues facing… Read More


DFM at SPIE Advance Litho show

DFM at SPIE Advance Litho show
by Beth Martin on 02-09-2012 at 6:40 pm

This year’s SPIE Advanced Lithography is loaded with interesting keynotes and sessions. To help me narrow down what to see, I spoke with John Sturtevant. John is co-chair of the Design for Manufacturability through Design-Process Integration conference, and the director for technical marketing for RET products at Mentor Graphics.… Read More


Design & Verification of Platform-Based, Multi-Core SoCs

Design & Verification of Platform-Based, Multi-Core SoCs
by Daniel Payne on 02-02-2012 at 11:16 am

Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More


The Future of Lithography Process Models

The Future of Lithography Process Models
by Beth Martin on 01-30-2012 at 4:02 pm

Always in motion is the future. ~Yoda

For nearly ten years now, full-chip simulation engines have successfully used process models to perform OPC in production. New full-chip models were regularly introduced as patterning processes evolved to span immersion exposure, bilayer resists, phase shift masking, pixelated illumination… Read More


SemiWiki and Mentor Graphics Seminar Series!

SemiWiki and Mentor Graphics Seminar Series!
by Daniel Nenni on 01-28-2012 at 10:49 am

For the greater good of the semiconductor ecosystem, SemiWiki and Mentor Graphics present SemiWiki Seminars, a free seminar and software demonstration series addressing the latest innovations in IC design. SemiWiki Seminars discuss interesting new challenges and potential solutions aimed at increased circuit density … Read More


Going up…3D IC design tools

Going up…3D IC design tools
by Paul McLellan on 01-23-2012 at 6:41 pm

3D and 2.5D (silicon interposer) designs create new challenges for EDA. Not all of them are in the most obvious areas. Mentor has an interesting presentation on what is required for verification and testing of these types of designs. Obviously it is somewhat Mentor-centric but in laying out the challenges it is pretty much agnostic.… Read More


What is a Hierarchical SPICE Circuit Simulator?

What is a Hierarchical SPICE Circuit Simulator?
by Daniel Payne on 01-19-2012 at 2:56 pm

Hierarchy is used in IC designs at many abstraction levels to help describe a design in a compact format:

  • Mask Data
  • IC Layout
  • Schematic Netlists
  • Gate level netlists
  • RTL netlists

But the question and focus for this blog is, “What is a hierarchical SPICE Circuit Simulator?”… Read More


Advanced Memory Cell Characterization with Calibre xACT 3D

Advanced Memory Cell Characterization with Calibre xACT 3D
by SStalnaker on 01-12-2012 at 7:18 pm

Advanced process technologies for manufacturing computer chips enable more functionality, higher performance, and low power through smaller sizes. Memory bits on a chip are predicted to double every two years to keep up with the demand for increased performance.

To meet these new requirements for performance and power, memory… Read More