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Mentor Shines at DVCon

Mentor Shines at DVCon
by Beth Martin on 02-18-2013 at 12:30 am

Mentor Graphics will be all over DVCon next week (February 25-28) at the DoubleTree hotel in San Jose.

In addition to attending all the panels, tutorials, posters, and the keynote, you can visit Mentor in booth 901 on the exhibit floor.
Here’s the lineup of Mentor-related events:… Read More


Magic? No! It’s Computational Lithography

Magic? No! It’s Computational Lithography
by Beth Martin on 02-11-2013 at 7:00 am

The industry plans to use 193nm light at the 20nm, 14nm, and 10nm nodes. Amazing, no? There is no magic wand; scientists have been hard at work developing computational lithography techniques that can pull one more rabbit out of the optical lithography hat.

Tortured metaphors aside, the goal for the post-tapeout flow is the same… Read More


Notes from Common Platform: Collaborate or Die

Notes from Common Platform: Collaborate or Die
by Beth Martin on 02-07-2013 at 2:16 pm

FinFETs are hot, carbon nanotubes are cool, and collaboration is the key to continued semiconductor scaling. These were the main messages at the 2013 Common Platform Technology Forum in Santa Clara.

The collaboration message ran through most presenations, like the afternoon talk by Subi Kengeri of GLOBALFOUNDRIES and Joe Sawicki… Read More


Mentor Snags Two Awards at DesignCon

Mentor Snags Two Awards at DesignCon
by Beth Martin on 01-29-2013 at 8:44 pm

Oh, awards season! The glitz! The glamour! The most important and innovative new design products!

That last part is a key feature of the annual DesignVision awards and the Best in Test awards presented at DesignCon 2013. Mentor Graphics’ test products scored two wins: a DesignVision award for their new Tessent IJTAG product, and… Read More


Get the Latest Info on DFM at the SPIE Litho Conference

Get the Latest Info on DFM at the SPIE Litho Conference
by glforte on 01-29-2013 at 2:12 pm

While the SPIE Advanced Lithography conference is best known for IC manufacturing, computational lithography, mask preparation and other back-end topics, there is also a significant amount of interest in Design for Manufacturing (DFM) at the conference because some litho issues are best (or only) addressed by modifying the… Read More


Time in a model: xtUML and concurrency

Time in a model: xtUML and concurrency
by Don Dingee on 01-27-2013 at 9:00 pm

Most embedded programming strategies involve decomposing the embedded application into chunks, which can then be executed as independent tasks. More advanced applications involve some type of data flow, and may attempt to execute operations in parallel where possible.… Read More


Cadence, Synopsys, and Mentor on FinFETs

Cadence, Synopsys, and Mentor on FinFETs
by Daniel Nenni on 01-27-2013 at 7:00 pm

In my opinion, FinFETs will be the most significant piece of technology we, as semiconductor ecosystem people, will experience this decade. Seriously this is exciting stuff and one of the top search terms on SemiWiki for 6 months running. Here is a quick peek at what the top EDA companies will be talking about at the Common PlatformRead More


First Time, Every Time

First Time, Every Time
by SStalnaker on 01-21-2013 at 7:10 pm

While this iconic advertising phrase was first used to describe the ink reliability of a ballpoint pen, it perfectly summarizes the average consumer’s attitude toward automobile reliability as well. We don’t really care how it’s done, as long as everything in our car works first time, every time. Even when that includes heated… Read More


Yawn… New EDA Leader Results Are Coming

Yawn… New EDA Leader Results Are Coming
by Randy Smith on 01-18-2013 at 4:00 pm

We will soon start to see the quarterly financial reporting installments of the “Big 3” public EDA companies. I predict they will be as boring as usual. I am not sure if I would want it any differently though.

Back in the 90s there were times when it was truly interesting to wait to see what Cadence, Mentor, or later Synopsys, might announce.… Read More


Fixing Double-patterning Errors at 20nm

Fixing Double-patterning Errors at 20nm
by Paul McLellan on 01-16-2013 at 10:54 pm

David Avercrombie of Mentor won the award for the best tutorial at the 2012 TSMC OIP for his presentation, along with Peter Hsu of TSMC, on Finding and Fixing Double Patterning Errors in 20nm. The whole presentation along with the slides is now available online here. The first part of the presentation is an introduction to double … Read More