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Q2FY24TessentAI 800X100
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Optimize AI Chips with Embedded Analytics

Optimize AI Chips with Embedded Analytics
by Kalar Rajendiran on 09-02-2021 at 6:00 am

Tessent Embedded Analytics Architecture

The foundry model, multi-source IP blocks, advanced packaging technologies, cloud computing, hyper-connectivity and access to open-source software have all contributed to the incredible electronics products of recent times. Along with this, the complexity of developing and taking a chip to market has also increased. And… Read More


AMS IC Designers need Full Tool Flows

AMS IC Designers need Full Tool Flows
by Daniel Payne on 08-31-2021 at 10:00 am

AMS tool flow min

Digital IC design gets a lot of attention, because all of our modern devices primarily use digital logic, but in reality whenever you have a sensor like a camera,  accelerometer, gyroscope or any radio like Bluetooth, WiFi or NFC, then you’re really in the realm of analog, and that’s where mixed-signal  IC design comes… Read More


Symmetry Requirements Becoming More Important and Challenging

Symmetry Requirements Becoming More Important and Challenging
by Tom Simon on 08-24-2021 at 10:00 am

Symmetry across the design flow

Humans certainly have always had an aesthetic preference for symmetry. We also see symmetry showing up frequently in nature. The importance of symmetry in electronic designs has been apparent for decades. There are a host of analog structures that require balanced layout. For instance, these include differential pairs and … Read More


Debugging Embedded Software on Veloce

Debugging Embedded Software on Veloce
by Bernard Murphy on 08-11-2021 at 6:00 am

Debugging Embedded Software on Veloce min

Arm provides great support for debugging embedded software in its CoreSight tools, but what support do you have if you’re debugging hardware and software together in a pre-implementation design? In a hardware debugger you have lots of support for hardware views like waveforms and register states. But these aren’t well connected… Read More


SoC Vulnerabilities

SoC Vulnerabilities
by Daniel Payne on 07-29-2021 at 6:00 am

side channel attack

As I read both the popular and technical press each week I often see articles about computer systems being hacked, and here’s just a few vulnerabilities from this week:

Read More

A Custom Layout Environment for SOC Design Closure

A Custom Layout Environment for SOC Design Closure
by Tom Simon on 07-22-2021 at 10:00 am

custom layout environment

Throughout the process of physical design and verification there are many groups working on the design. Most often these groups are working independently or in parallel but separately, using their own specialized tools, such as P&R, DRC, custom layout, DFM, etc. At the end of the process there is an inevitable requirement… Read More


Siemens Offers Insights into Gate Level CDC Analysis

Siemens Offers Insights into Gate Level CDC Analysis
by Tom Simon on 06-28-2021 at 10:00 am

CDC Analysis

Glitches on clock domain crossing signals have always been a concern for chip designers. Now with increased requirements for reliability, renewed scrutiny is being given to find ways to identify these problems and fix them. In particular applications such as automotive electronics have given this added effort an impetus. Siemens… Read More


RealTime Digital DRC Can Save Time Close to Tapeout

RealTime Digital DRC Can Save Time Close to Tapeout
by Tom Simon on 06-07-2021 at 6:00 am

RealTime DRC

Over the years DRC tools have done an admirable job of keeping pace with the huge growth of IC design size. Yet, DRC runs for sign off on the full design using foundry rule decks take many hours to complete. These long run times are acceptable for final sign off, but there are many situations where DRC results are needed quickly when small… Read More


From Silicon To Systems

From Silicon To Systems
by Daniel Payne on 05-31-2021 at 10:00 am

digitalization min

The annual Siemens Digital Industries Software user group event was held virtually on May 26th, which made it easy to attend from my home office, although selecting from the list of speakers was a challenge, because they offered 475 sessions, wow. My focus is EDA, so I listened to Joseph Sawicki, the Executive Vice President, IC … Read More


Heterogeneous Chiplets Design and Integration

Heterogeneous Chiplets Design and Integration
by Kalar Rajendiran on 05-28-2021 at 6:00 am

Transistor Cost per Billion 3nm Projection

Over the recent years, the volume and velocity of discussions relating to chiplets have intensified. A major reason for this is the projected market opportunity. According to research firm Omdia, chiplets driven market is expected to be $6B by 2024 from just $645M in 2018. That’s an impressive nine-fold projected increase over… Read More