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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4342
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4342
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Mentor Acquires Magma?

Mentor Acquires Magma?
by Daniel Nenni on 11-21-2010 at 5:39 pm

**This blog was written a year ago. Several people emailed me last week saying Mentor is trying for Magma again so I thought I would run it again to see what we can find out!D.A.N. 11/21/2011

“I believe that within five years only two EDA companies will survive,” said Magma Design Automation Rajeev Madhavan (Silicom Ventures LLC internationalRead More


Computational Lithography, Scaling’s Best Friend

Computational Lithography, Scaling’s Best Friend
by glforte on 11-03-2010 at 11:51 pm

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By Joseph Sawicki, Vice President & General Manager, Design to Silicon Division

It is one of the more amazing stories in the continued march of Moore’s Law over the past four nodes. Previously scaling was enabled solely though changes in the physical domain, whether through decreasing the wavelength of light, increasing … Read More


What Do You Mean by Mandatory?

What Do You Mean by Mandatory?
by glforte on 10-14-2010 at 6:00 pm

When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” … Read More


What Do You Mean by Mandatory?

What Do You Mean by Mandatory?
by glforte on 10-14-2010 at 6:00 pm

When TSMC and Mentor Graphics held a joint seminar for mutual customers to go over new DFM requirements at 45/40 nm, two customers basically asked the same question, “What do you mean by mandatory?” Of course, TSMC wasn’t going to stand over them and say, “Mandatory means mandatory, what part of mandatory don’t you understand?” … Read More


How to Multi-Voltage IC Design in 10 Easy Steps

How to Multi-Voltage IC Design in 10 Easy Steps
by glforte on 10-14-2010 at 4:14 pm

What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:… Read More


Clocks Will Be Clocks

Clocks Will Be Clocks
by glforte on 10-14-2010 at 4:14 pm

Clock designers are an enigma. Clock designers in general are die hard Star Wars fans, own vintage Porsches that leak oil by the gallon, usually have lava lamps in their offices/cubicles, wear fancy leather jackets in the peak of summer, and have like-minded clock designers as best lunch buddies. … Read More


Why Only MV When You Can MC, MM & MV?

Why Only MV When You Can MC, MM & MV?
by glforte on 10-14-2010 at 4:14 pm

Resistance is futile. I recently caved and switched to an iPhone after having been a loyal Google phone user for more than year. Apart from the coolness factor, my main motivation was corporate mail support that was absent in Gphone, plus the fact that I got the iPhone for free when my wife upgraded hers. The difference is day and night… Read More


How to Multi-Voltage IC Design in 10 Easy Steps

How to Multi-Voltage IC Design in 10 Easy Steps
by glforte on 10-14-2010 at 4:14 pm

What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:… Read More


So, Why Not Just Write Better Rules?

So, Why Not Just Write Better Rules?
by glforte on 10-14-2010 at 4:00 pm

In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.… Read More