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EDA

Electronic Design Automation

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Want to learn Mixed-Signal Design and Verification?

Want to learn Mixed-Signal Design and Verification?
by Daniel Payne on 07-20-2011 at 6:13 pm
Categories: EDA, Siemens EDA

Workshops are a great where to learn hands-on about IC design technology. Mentor has a free workshop to introduce you to creating, simulating and verifying mixed-signal (Analog and Digital) designs.

PLL waveforms showing both digital and analog signals.

Dates in Fremont, California
July 26, 2011
September 15, 2011
November… Read More

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Gary Smith on the Apache acquisition

Gary Smith on the Apache acquisition
by Paul McLellan on 07-20-2011 at 4:44 pm
Categories: Ansys, Inc., EDA

Gary Smith has a note out about the Apache acquisition by Ansoft (unfortunately if you get his email newsletter the link there takes you to the wrong article but it really is here or here as pdf). Most of the note actually describes the acquisition and the Apache product line which won’t reveal much new to anyone here.

He regards… Read More

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Oasys’s customers

Oasys’s customers
by Paul McLellan on 07-20-2011 at 1:36 pm
Categories: EDA

I haven’t made a secret of the fact that I maintain Oasys Design System’s website. So I had a small task yesterday of adding Qualcomm to the list of customer logos that cycle through on the home page. It is a pretty impressive list including Juniper Networks, Netlogic Microsystems, Texas Instruments and ST Microelectronics.… Read More

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EDA Consortium Newsletter, Q1 2011

EDA Consortium Newsletter, Q1 2011
by Daniel Payne on 07-19-2011 at 1:08 pm
Categories: EDA

Each quarter, the EDA Consortium publishes the Market Statistics Service (MSS) report containing detailed revenue data for the EDA industry. The report compiles data submitted confidentially by both public and private EDA companies into tables and charts listing the data by both EDA category and geographic region. This newsletter… Read More

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Synopsys Virtualizer

Synopsys Virtualizer
by Paul McLellan on 07-19-2011 at 8:00 am
Categories: EDA, Synopsys

As you probably know, Synopsys last year acquired VaST and CoWare and a couple of years early had acquired Virtio. All three companies primarily competed in the virtual platform market. In addition, Synopsys is the #2 IP company (behind ARM) and has a wide range of tools for SoC design. So the interesting question is how would they… Read More

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Variation Analysis

Variation Analysis
by Paul McLellan on 07-18-2011 at 1:33 pm
Categories: EDA, Solido

I like to say that “you can’t ignore the physics any more” to point out that we have to worry about lots of physical effects that we never needed to consider. But “you can’t ignore the statistics any more” would be another good slogan. In the design world we like to pretend that the world is pass/fail. But manufacturing is actually a statistical… Read More

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Richard Goering does Q&A with ClioSoft CEO

Richard Goering does Q&A with ClioSoft CEO
by Daniel Payne on 07-18-2011 at 11:05 am
Categories: Cadence, Cliosoft, EDA

Richard Goering is well-known from his editorial days at EE Times (going back some 25 years), now at Cadence he blogs at least once a week on EDA topics that touch Cadence tools.

Before DAC he talked with Srinath Anantharaman about how Cadence tools work together with ClioSoft tools to keep IC Design Data Management Simple.

Through… Read More

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Webinar: IP integration methodology

Webinar: IP integration methodology
by Paul McLellan on 07-17-2011 at 12:24 pm
Categories: Ansys, Inc., EDA

The next Apache webinar is coming up on 21st July at 11am Pacific time on “IP integration methodology”.

This webinar will be conducted by Arvind Shanmugavel, Director Applications Engineering at Apache Design Solutions. Mr. Shanmugavel has been with Apache since 2007, supporting the RedHawk and Totem product … Read More

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First low-power webinar: Ultra-low-power Methodology

First low-power webinar: Ultra-low-power Methodology
by Paul McLellan on 07-13-2011 at 12:10 pm
Categories: Ansys, Inc., EDA

The first of the low power webinars is coming up on July 19th at 11am Pacific time. The webinar will be conducted by Preeti Gupta, Sr. Technical Marketing Manager at Apache Design Solutions. Preeti has 10 years of experience in the exciting world of CMOS power. She has a Masters in Electrical Engineering from Indian Institute of technology,… Read More

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Cadence aquires Azuro

Cadence aquires Azuro
by Paul McLellan on 07-12-2011 at 12:20 pm
Categories: Cadence, EDA

Cadence this morning announced that it has acquired Azuro. Azuro has become a leader in building the clock trees for high performance SoCs. A good rule of thumb is that the clock consumes 30% of the power in an SoC so optimizing it is really important. Terms were not disclosed.

The clock trees involve clock gating which can reduce clock… Read More