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Electronic Design Automation
Although design for manufacturing (DFM) tools and techniques have been around for several nodes, a lot of designers remain skeptical about their actual value, especially since many products still make it successfully to market without the use of DFM.… Read More
Unmanned systems are becoming indispensable to military forces and are used across all of land, sea and air. The generic name for such unmanned systems is UXS, usually UAS (air), UGS (ground) or UUS (underwater). The UAS is the most visible, both due to military strikes and the views of Japan after the Tsunami when areas were unreachable… Read More
As part of the DFM Conference at the SPIE Advance Lithography symposium, the DFM committee is conducting an informal survey on the current state of Design For Manufacturability in the Semiconductor Industry.
Please take this anonymous 16 question survey to identify critical Design for Manufacturability (DFM) issues facing… Read More
I have been saying for years, ever since I started working at VaST, the biggest barrier to adoption of virtual platform technology for what I like to call virtualized software development is the availability of models. If models do not already exist when they are needed there are two issues: it takes money to develop them but, probably… Read More
This year’s SPIE Advanced Lithography is loaded with interesting keynotes and sessions. To help me narrow down what to see, I spoke with John Sturtevant. John is co-chair of the Design for Manufacturability through Design-Process Integration conference, and the director for technical marketing for RET products at Mentor Graphics.… Read More
The EDAC Emerging Companies Comittee (would that be the EDACECC?) is organizing a free panel session one evening at DVCon. It is Monday February 27th from 6pm to 8.30pm. I don’t yet have a room but it will be at the DoubleTree Hotel where DVCon is being held.
EDA companies often address hardware/software co-design from a hardware… Read More
Things you don’t know about Virtuoso: we’ve got you cornered.
That is the title on a Cadence blog item last week. It is actually about variability and how to create various corners for simulation and analysis, but given Cadence’s franchise for Virtuoso, its lock-in through SKILL-based PDKs and so forth, it … Read More
Even if ExpertIO acquisition by Synopsys, coming after nSys acquisition a couple of months ago, will not have a major impact on Synopsys’ balance sheet, it will again change the Verification IP market landscape. The acquisition of Inventure, a subsidiary of Zuken, will have a major impact on the Interface IP market, even if it’s… Read More
At DVCon on Thursday March 1st (St David’s day for any Welsh readers) Jasper is sponsoring lunch from 12pm to 1.30pm. It will take place in the Cascade/Sierra ballrooms.
During lunch there will be a panel discussion Formal Verification from Users’ Perspectives with real users no how they mitigate risk in their designs… Read More
On my last graphics chip design at Intel the project manager asked me, “So, will this new chip work when silicon comes back?”
My response was, “Yes, however only the parts that we have been able to simulate.”
Today designers of semiconductor IP and SoC have more approaches than just simulation to ensure… Read More
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Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business