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Sagantec 2 Migrate iPad2s @ #48DAC

Sagantec 2 Migrate iPad2s @ #48DAC
by admin on 05-30-2011 at 2:53 pm

Sagantec is the leading EDA provider of process migration solutions for custom IC design. Sagantec’s EDA solutions enable IC designers to leverage their investment in existing physical design IP and accomplish dramatic time and effort savings in the implementation of custom, analog, mixed-signal and memory circuits… Read More


New TSMC 28nm Design Ecosystem!

New TSMC 28nm Design Ecosystem!
by Daniel Nenni on 05-28-2011 at 9:23 pm

TSMC rolled out the new reference flows for 28nm design as part of the Open Innovation Platform. The biggest surprise (to me) is that Cadence is STILL in the TSMC reference flows!

The updated TSMC OIP wiki is here, the Reference Flow 12.0 wiki can be found here, the AMS 2.0 reference flow wiki is here, and the official TSMC PR is here. Read More


3D IC @ #48DAC

3D IC @ #48DAC
by Daniel Nenni on 05-23-2011 at 4:54 pm

A three-dimensional integrated circuit (3D IC ) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is hotly pursuing this emerging technology in many different forms, as a result the full definition is still somewhat… Read More


48th Annual Design Automation Conference

48th Annual Design Automation Conference
by Daniel Nenni on 05-23-2011 at 8:08 am

The 48[SUP]th[/SUP] Design Automation Conference (DAC) is now upon us. DAC is billed as “the premier event for the design of electronic circuits and systems, and for EDA and silicon solutions” for which I would have to agree with 100%.

The first DAC I attended was in 1984, Albuquerque New Mexico, which was one of the first to allow … Read More


Analyzing and Planning Electro-static Discharge (ESD) Protection

Analyzing and Planning Electro-static Discharge (ESD) Protection
by Paul McLellan on 05-23-2011 at 5:00 am

ESD has historically been a big problem analyzed with ad-hoc approaches. As explained earlier, this is no longer an adequate way to plan nor signoff ESD protection.

Pathfinder is the first full-chip comprehensive ESD planning and verification solution. It is targeted to address limitations in today’s methodologies.… Read More


Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review

Cadence Virtuoso 6.1.5 and ClioSoft Hardware Configuration Management – Webinar Review
by Daniel Payne on 05-19-2011 at 5:33 pm

Introduction
Cadence and ClioSoft made a webinar recently and I’ll summarize what I learned from it.

What’s New from Cadence in Virtuoso 6.1.5

  • Back2Basics (28nm rule integration, Skill improved with object-oriented, OASIS support, HTML Publisher, Waveform re-written for better Analog support, smaller Waveform
Read More

A New Hierarchical 3D Field Solver

A New Hierarchical 3D Field Solver
by Daniel Payne on 05-19-2011 at 2:04 pm

Introduction
3D field solvers produce the most accurate netlists of RC values of your IC layout that can then be used in SPICE circuit simulators however most of these solvers produce a flat netlist which tends to simulate rather slowly. Thankfully several years ago the first hierarchical SPICE tools were offered by Nassda (HSIMRead More


Electro-static Discharge (ESD)

Electro-static Discharge (ESD)
by Paul McLellan on 05-18-2011 at 4:26 pm

Electro-static discharge (ESD) has been a problem since the beginning of IC production. Chips function on power supplies of up to a few volts (depending on the era) whereas ESD voltages are measured in the thousands of volts. When you reach out for your car door handle and a spark jumps across, that is ESD. If you were touching a chip… Read More


Shakeup at Mentor Graphics

Shakeup at Mentor Graphics
by Daniel Payne on 05-12-2011 at 12:22 pm

Reading the title you guessed it right, Mentor Graphics has three new board members today from the slate offered by billionaire activist Carl Icahn:

  • José Maria Alapont, chief executive of the auto parts maker Federal-Mogul
  • Gary Meyers, a director of the chip maker Exar
  • David Schechter, an executive at Mr. Icahn’s investment firm
Read More

SOC Realization: How Chips Are Really Designed

SOC Realization: How Chips Are Really Designed
by Paul McLellan on 05-09-2011 at 10:00 pm

If you just casually peruse most marketing presentations by EDA companies, you’d come to the conclusion most SoCs are designed from scratch, wrestlilng the monster to the ground with bare hands. But the reality is that most SoCs consist of perhaps 90% IP blocks (many of them memories). That still leaves the remaining 10% … Read More