Synopsys Multi Die Webinar 800x100
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EDA

Electronic Design Automation

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Variation Analysis

Variation Analysis
by Paul McLellan on 07-18-2011 at 1:33 pm
Categories: EDA, Solido

I like to say that “you can’t ignore the physics any more” to point out that we have to worry about lots of physical effects that we never needed to consider. But “you can’t ignore the statistics any more” would be another good slogan. In the design world we like to pretend that the world is pass/fail. But manufacturing is actually a statistical… Read More

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Richard Goering does Q&A with ClioSoft CEO

Richard Goering does Q&A with ClioSoft CEO
by Daniel Payne on 07-18-2011 at 11:05 am
Categories: Cadence, Cliosoft, EDA

Richard Goering is well-known from his editorial days at EE Times (going back some 25 years), now at Cadence he blogs at least once a week on EDA topics that touch Cadence tools.

Before DAC he talked with Srinath Anantharaman about how Cadence tools work together with ClioSoft tools to keep IC Design Data Management Simple.

Through… Read More

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Webinar: IP integration methodology

Webinar: IP integration methodology
by Paul McLellan on 07-17-2011 at 12:24 pm
Categories: Ansys, Inc., EDA

The next Apache webinar is coming up on 21st July at 11am Pacific time on “IP integration methodology”.

This webinar will be conducted by Arvind Shanmugavel, Director Applications Engineering at Apache Design Solutions. Mr. Shanmugavel has been with Apache since 2007, supporting the RedHawk and Totem product … Read More

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First low-power webinar: Ultra-low-power Methodology

First low-power webinar: Ultra-low-power Methodology
by Paul McLellan on 07-13-2011 at 12:10 pm
Categories: Ansys, Inc., EDA

The first of the low power webinars is coming up on July 19th at 11am Pacific time. The webinar will be conducted by Preeti Gupta, Sr. Technical Marketing Manager at Apache Design Solutions. Preeti has 10 years of experience in the exciting world of CMOS power. She has a Masters in Electrical Engineering from Indian Institute of technology,… Read More

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Cadence aquires Azuro

Cadence aquires Azuro
by Paul McLellan on 07-12-2011 at 12:20 pm
Categories: Cadence, EDA

Cadence this morning announced that it has acquired Azuro. Azuro has become a leader in building the clock trees for high performance SoCs. A good rule of thumb is that the clock consumes 30% of the power in an SoC so optimizing it is really important. Terms were not disclosed.

The clock trees involve clock gating which can reduce clock… Read More

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Design for test at RTL

Design for test at RTL
by Paul McLellan on 07-10-2011 at 3:09 pm
Categories: EDA

Design for test (DFT) imposes various restrictions on the design so that the test automation tools (automatic test pattern approaches such as scan, as well as built-in self-test approaches) will subsequently be able to generate the test program. For example, different test approaches impose constraints on clock generation… Read More

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Low Power Webinar Series

Low Power Webinar Series
by Paul McLellan on 07-08-2011 at 4:57 pm
Categories: Ansys, Inc., EDA

At DAC 2011 in San Diego, Apache gave many product presentations. Of course not everyone could make DAC or could make all the presentations in which they were interested. So from mid-July until mid-August these presentations will be given as webinars. Details, and links for registration, are here on the Apache website.

The seminars… Read More

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Apache Design Automation acquired by Ansys

Apache Design Automation acquired by Ansys
by Daniel Payne on 06-30-2011 at 2:52 pm
Categories: Ansys, Inc., EDA

We all knew that Apache had filed for an IPO earlier and were just waiting for the timing and price to be revealed. Rumors have been circulating about an acquisition and today we know that the rumors were true asAnsys paid $310 million in cash for Apache.

Ansys stock has surged some 35% over the past twelve months:

Products
This acquisition… Read More

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SOC Realization

SOC Realization
by Paul McLellan on 06-27-2011 at 5:28 pm
Categories: EDA

There are some very interesting comments to the last entry on SoC Realization and how more and more chips are actually assembled out of IP. There was clearly a lot of discussion in this area at DAC, although most people (Atrenta being an exception) don’t use the term SoC Realization, presumably because it was originated by … Read More

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ARM and Mentor Team Up on Test

ARM and Mentor Team Up on Test
by Daniel Payne on 06-27-2011 at 2:31 pm
Categories: Arm, EDA, IP, Siemens EDA

Introduction
Before DAC I met with Stephen Pateras, Ph.D. at Mentor Graphics, he is the Product Marketing Director in the Silicon Test Solutions group. Stephen has been at Mentor for two years and was part of the LogicVision acquisition. He was in early at LogicVision and went through their IPO, before that he was at IBM in the mainframe… Read More