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DFM Industry Survey

DFM Industry Survey
by Beth Martin on 02-10-2012 at 1:28 pm

As part of the DFM Conference at the SPIE Advance Lithography symposium, the DFM committee is conducting an informal survey on the current state of Design For Manufacturability in the Semiconductor Industry.

Please take this anonymous 16 question survey to identify critical Design for Manufacturability (DFM) issues facing… Read More


Yes, there is such a thing as a free…model

Yes, there is such a thing as a free…model
by Paul McLellan on 02-09-2012 at 8:18 pm

I have been saying for years, ever since I started working at VaST, the biggest barrier to adoption of virtual platform technology for what I like to call virtualized software development is the availability of models. If models do not already exist when they are needed there are two issues: it takes money to develop them but, probably… Read More


DFM at SPIE Advance Litho show

DFM at SPIE Advance Litho show
by Beth Martin on 02-09-2012 at 6:40 pm

This year’s SPIE Advanced Lithography is loaded with interesting keynotes and sessions. To help me narrow down what to see, I spoke with John Sturtevant. John is co-chair of the Design for Manufacturability through Design-Process Integration conference, and the director for technical marketing for RET products at Mentor Graphics.… Read More


DVCon: Hardware/software Co-design from a Software Perspective

DVCon: Hardware/software Co-design from a Software Perspective
by Paul McLellan on 02-09-2012 at 4:56 am

The EDAC Emerging Companies Comittee (would that be the EDACECC?) is organizing a free panel session one evening at DVCon. It is Monday February 27th from 6pm to 8.30pm. I don’t yet have a room but it will be at the DoubleTree Hotel where DVCon is being held.

EDA companies often address hardware/software co-design from a hardware… Read More


Virtuoso has got you cornered

Virtuoso has got you cornered
by Paul McLellan on 02-07-2012 at 1:33 pm

Things you don’t know about Virtuoso: we’ve got you cornered.

That is the title on a Cadence blog item last week. It is actually about variability and how to create various corners for simulation and analysis, but given Cadence’s franchise for Virtuoso, its lock-in through SKILL-based PDKs and so forth, it … Read More


Synopsys latest acquisitions: ExpertIO (VIP) and Inventure (IP)… Any counter-attack from Cadence?

Synopsys latest acquisitions: ExpertIO (VIP) and Inventure (IP)… Any counter-attack from Cadence?
by Eric Esteve on 02-07-2012 at 12:29 pm


Even if ExpertIO acquisition by Synopsys, coming after nSys acquisition a couple of months ago, will not have a major impact on Synopsys’ balance sheet, it will again change the Verification IP market landscape. The acquisition of Inventure, a subsidiary of Zuken, will have a major impact on the Interface IP market, even if it’s… Read More


DVCon: Formal Verification with lunch

DVCon: Formal Verification with lunch
by Paul McLellan on 02-03-2012 at 6:03 pm

At DVCon on Thursday March 1st (St David’s day for any Welsh readers) Jasper is sponsoring lunch from 12pm to 1.30pm. It will take place in the Cascade/Sierra ballrooms.

During lunch there will be a panel discussion Formal Verification from Users’ Perspectives with real users no how they mitigate risk in their designs… Read More


Using "Apps" to Take Formal Analysis Mainstream

Using "Apps" to Take Formal Analysis Mainstream
by Daniel Payne on 02-02-2012 at 12:47 pm

2760d1328206331 dvcon 2012.png

On my last graphics chip design at Intel the project manager asked me, “So, will this new chip work when silicon comes back?”

My response was, “Yes, however only the parts that we have been able to simulate.”

Today designers of semiconductor IP and SoC have more approaches than just simulation to ensure… Read More


Design & Verification of Platform-Based, Multi-Core SoCs

Design & Verification of Platform-Based, Multi-Core SoCs
by Daniel Payne on 02-02-2012 at 11:16 am

Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More


3D Standards

3D Standards
by Paul McLellan on 02-01-2012 at 5:06 pm

At DesignCon this week there was a panel on 3D standards organized by Si2. I also talked to Aveek Sarkar of Apache (a subsidiary of Ansys) who is one of the founding member companies of the Si2 Open3D Technical Advisory Board (TAB), along with Atrenta, Cadence, Fraunhofer Institute, Global Foundries, Intel, Invarian, Mentor, Qualcomm,… Read More