CAST Compression IP Webinar 800x100 (2)
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SPIE 2023 Buzz – Siemens Aims to Break Down Innovation Barriers by Extending Design Technology Co-Optimization

SPIE 2023 Buzz – Siemens Aims to Break Down Innovation Barriers by Extending Design Technology Co-Optimization
by Mike Gianfagna on 12-26-2023 at 6:00 am

SPIE 2023 Buzz – Siemens Aims to Break Down Innovation Barriers by Extending Design Technology Co Optimization

Preventing the propagation of systematic defects in today’s semiconductor design-to-fabrication process requires many validation, analysis and optimization steps. Tools involved in this process can include design rule checking (DRC), optical proximity correction (OPC) verification, mask writing and wafer printing… Read More


Preventing SOC Schedule Delays Using the Cloud

Preventing SOC Schedule Delays Using the Cloud
by Ronen Laviv on 12-25-2023 at 6:00 am

compute peaks 1

In my previous article, we touched on ways to pull in the schedule. This time I’d like to analyze how peak usage affects project timeline and cost. The above graph is based on real pattern taken from one development week in Annapurna Labs 5nm Graviton.

The Graph shows the number of variable servers per hour per day. There’s a baseline… Read More


Giving Back – The Story of One Silicon Valley Veteran’s Journey

Giving Back – The Story of One Silicon Valley Veteran’s Journey
by Mike Gianfagna on 12-22-2023 at 6:00 am

Giving Back – The Story of One Silicon Valley Veteran’s Journey

The concept of giving back is something many of us have contemplated. Giving back to the community or to support a particular cause. How to respond to those inquiries from our alma mater is another example. These conversations typically focus on giving money to provide needed support. As engineers, we are surrounded by a massive… Read More


RISC-V and Chiplets: A Panel Discussion

RISC-V and Chiplets: A Panel Discussion
by Paul McLellan on 12-13-2023 at 10:00 am

rvnames

At the recent RISC-V Summit, the very last session was a panel about chiplets called Chiplets in the RISC-V Ecosystem. It was moderated by Calista Redmond, the CEO of RISC-V International. The panelists were:

  • Laurent Moll, COO of Arteris
  • Aniket Saha, VP of Product Management of Tenstorrent
  • Dale Greenley, VP of Engineering of Ventana
Read More

Using PCB Automation for an AI and Machine Vision Product

Using PCB Automation for an AI and Machine Vision Product
by Daniel Payne on 12-12-2023 at 10:00 am

machine vision testing

I knew that HDMI was a popular standard used to connect consumer products like a monitor to a laptop, but most professional video and broadcast systems use the SDI (Serial Digital Interface) connector standard. Pleora Technologies, founded in 2000, currently serves the machine vision and manufacturing markets, including those… Read More


Automated Constraints Promotion Methodology for IP to Complex SoC Designs

Automated Constraints Promotion Methodology for IP to Complex SoC Designs
by Kalar Rajendiran on 12-12-2023 at 6:00 am

Synopsys Timing Constraints Manager

In the world of semiconductor design, constraints are essentially specifications and requirements that guide the implementation of a specific hardware or software component within a larger system. They dictate timing, area, power, performance, and of course functionality of a design, playing a crucial role in ensuring that… Read More


WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems

WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems
by Daniel Nenni on 12-11-2023 at 10:00 am

Blog UPF Picture1

Nowadays, low power design requirements are key for large SoCs (system on chips) for different applications: AI, Mobile, HPC, etc. Power intent management early in the design flow is becoming crucial to help facing PPA (Power Performance Area) design challenges.

WEBINAR REGISTRATION

With the increasing complexity of such … Read More


UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
by Kalar Rajendiran on 12-11-2023 at 6:00 am

Pike Creek UCIe Test chip

Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More


Analysis and Verification of Single Event Upset Mitigation

Analysis and Verification of Single Event Upset Mitigation
by Jacob Wiltgen on 12-07-2023 at 10:00 am

Figure 1 Driving trends

The evolution of space-based applications continues to drive innovation across government and private entities. The new demands for advanced capabilities and feature sets have a direct impact on the underlying hardware, driving companies to migrate to smaller geometries to deliver the required performance, area, and power… Read More


Do you have Time to Pull in your Tapeout Schedule?

Do you have Time to Pull in your Tapeout Schedule?
by Ronen Laviv on 12-06-2023 at 10:00 am

schedule pullin

So… , we’re 4 months before tapeout. You were assigned to close place & route on three complex key blocks. You have 15 machines for the job, 5 per block.

You send your first batch, 5 runs per block. You’re not very surprised that your first batch fails. You modify the scripts, and run another batch. And… (Surprise… Read More