Image censoring with radio frequency (RF) in CMOS is a combination of light sensing chips and wireless communication. Typically, we were first engaged in the article, “RF Design Issues and Challenges in a CMOS Image Sensor Process”, because of the circuit design process required to make a functioning Radio Frequency transceiver.… Read More
Electronic Design Automation
Managing and Reusing IP in a Build-Borrow-Buy Era
Make-versus-buy inadequately describes what we do now in electronic systems design. We are on a continuum of design IP acquisition and use decisions, often with a portfolio of active projects and future projects depending on the outcome. Properly managing IP means adopting a build-borrow-buy mindset and tools capable of handling… Read More
IoT or Smart Everything?
I just attended a keynote presentation at SNUG from Aart de Geus, CEO of Synopsys. This event is well attended with some 2,500 people that are learning from the 96 presentations on all things Synopsys, semiconductor. IP, and foundry trends. There are big name sponsors like: GLOBALFOUNDRIES, Samsung, socioeconomic, TSMC, Fujitsu,… Read More
The Latest in Static Timing Analysis with Variation Modeling
In many ways, static timing analysis (STA) is more of an art than a science. Methodologists are faced with addressing complex phenomena that impact circuit delay — e.g., signal crosstalk, dynamic I*R supply voltage drop, temperature inversion, device aging effects, and especially (correlated and uncorrelated) process… Read More
Bridging Design Environments for Advanced Multi-Die Package Verification
This year is shaping up to be an inflection point, when multi-die packaging technology will experience tremendous market growth. Advanced 2.5D/3D package offerings have been available for several years, utilizing a variety of technologies to serve as the package substrate, interposer material for embedding die micro-bump… Read More
IC Design Optimization for Radiation Hardening
I was born in 1957, the same year that the Soviets launched the first satellite into Earth orbit, officially starting the Space Race between two global super powers. Today there are many countries engaged in space research and I just read about how engineers at IEAv (Institute for Advanced Studies) in Brazil did their IC design optimization… Read More
Improvements in SRAM Yield Variation Analysis
The design of an SRAM array requires focus on the key characteristics of readability, writeability, and read stability. As technology scaling has enabled the integration of large (cache) arrays on die, the sheer number of bitcells has necessitated a verification methodology that focuses on “statistical high-sigma” variation… Read More
Webinar: A Tool for Process and Device Evaluation
Not only are foundries continuing to introduce processes at new advanced nodes, they are frequently updating or adding processes at existing nodes. There are many examples that illustrate this well. TSMC now has 16FF, 16FF+ and now 16FFC. They are also announcing 10nm and 7nm processes. In addition, they are going back to older… Read More
SystemC and Adam’s Law
At DVCon I sat in on a series of talks on using higher-level abstraction for design, then met Adam Sherer to get his perspective on progress in bringing SystemC to the masses (Adam runs simulation-based verification products at Cadence and organized the earlier session). I have to admit I have been a SystemC skeptic (pace Gary Smith)… Read More
What SOC Size Growth Means for IP Management
Whether or not in the past you believed all the of rhetoric about exploding design complexity in SOC’s, today there can be no debate that SOC size and complexity is well beyond something that can be managed without some kind of design management system. As would be expected, development of most larger designs relies on a data management… Read More
AI RTL Generation versus AI RTL Verification