Banner Electrical Verification The invisible bottleneck in IC design updated 1
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EDA

Electronic Design Automation

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Neural Networks Poised to Make Big Changes in Our World

Neural Networks Poised to Make Big Changes in Our World
by Tom Simon on 04-11-2016 at 12:00 pm
Categories: Cadence, EDA

Probably the most interesting thing about Neural Networks is how they can be used for complex recognition tasks that we as people can easily perform but we might have a lot of trouble explaining how. One very good example of a problem that Neural Networks can tackle is determining when people are making a fake smile. Intuitively we… Read More

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Custom Layout Productivity Gets a Boost

Custom Layout Productivity Gets a Boost
by Tom Dillinger on 04-11-2016 at 7:00 am
Categories: EDA, Synopsys

In the 1970’s, when Moore’s Law was still in its infancy, Bill Lattin from Intel published a landmark paper [1]. In it he identified the need for new design tools and methods to improve layout productivity, which he defined as the drawn and verified number of transistors per day per layout designer. He said existing … Read More

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The Importance of Transistor-Level Verification

The Importance of Transistor-Level Verification
by admin on 04-10-2016 at 7:00 am
Categories: EDA

According to the IEEE Std 1012-2012, verification is the acknowledgement that a product is in satisfactory condition by meeting a set of rigorous criteria. [3] Transistor-level verification involves the use of custom libraries and design models to achieve ultimate performance, low power, or layout density. [2] Prediction… Read More

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Webinar alert – Taking UVM to the FPGA bank

Webinar alert – Taking UVM to the FPGA bank
by Don Dingee on 04-08-2016 at 4:00 pm
Categories: Aldec, EDA

UVM has become a preferred environment for functional verification. Fundamentally, it is a host based software simulation. Is there a way to capture the benefits of UVM with hardware acceleration on an FPGA-based prototyping system? In an upcoming webinar, Doulos CTO John Aynsley answers this with a resounding yes.… Read More

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3D TCAD Simulation of Silicon Power Devices

3D TCAD Simulation of Silicon Power Devices
by Daniel Payne on 04-07-2016 at 12:00 pm
Categories: EDA, FinFET

Process and device engineers are some of the unsung heroes in our semiconductor industry that have the daunting task of figuring out how to actually create a new process node that will fit some specific, market niche with sufficient yield to make their companies profitable and stand out from the competition. One such market segment… Read More

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The Most Important Point You May Have Missed at CDNLive 2016!

The Most Important Point You May Have Missed at CDNLive 2016!
by Daniel Nenni on 04-06-2016 at 4:00 am
Categories: Cadence, EDA

This was the best keynote lineup I can remember at a user group meeting. All four speakers are visionaries but from very different perspectives. The video of the event will be up later this month but from my first count the word “System(s)” was mentioned 32 times and the underlying message will transform the semiconductor industry… Read More

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Innovation in Transistor Design with Carbon Nanotubes

Innovation in Transistor Design with Carbon Nanotubes
by Students@olemiss.edu on 04-05-2016 at 4:00 pm
Categories: EDA

The New York Times article “IBM Scientists Find New Way to Shrink Transistors” by John Markoff focuses on the goal of the semiconductor industry to create smaller transistors in order to remain competitive while emphasizing cutting-edge design strategies with the use of carbon nanotubes. By switching from traditional methods… Read More

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Analog Design Verification — Traceability is Required

Analog Design Verification — Traceability is Required
by Tom Dillinger on 04-05-2016 at 9:45 am
Categories: Cadence, EDA

Digital verification engineers have developed robust, thorough metrics for evaluating design coverage. Numerous tools are available to evaluate testbenches against RTL model descriptions — e.g., confirming that simulation regressions exhaustively exercise signal toggles, RTL statement lines, individual statement… Read More

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PCB Design Requires Both Speed and Accuracy of SI/PI Analysis

PCB Design Requires Both Speed and Accuracy of SI/PI Analysis
by Tom Dillinger on 04-04-2016 at 8:00 am
Categories: EDA, Siemens EDA

The prevailing industry trends are clear: (1) PCB and die package designs are becoming more complex, across both mobile and high-performance applications; (2) communication interface performance between chips (and their related protocols) is increasingly demanding to verify; (3) signal integrity and power integrity issues… Read More