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EDA

Electronic Design Automation

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AMD Forms China X86 Server Chip Joint Venture

AMD Forms China X86 Server Chip Joint Venture
by Patrick Moorhead on 05-13-2016 at 4:00 pm
Categories: EDA

We have written a lot of research and notes about the China server market and their unique needs as it relates to security and intellectual property and the ways western server OEMs and chipmakers like Intel, Advanced Micro Devices, ARM Holdings, Qualcomm and IBM’s OpenPOWER are addressing the challenge.

Basically, China wants… Read More

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Getting Low Power Design Right in Mixed Signal Designs

Getting Low Power Design Right in Mixed Signal Designs
by Bernard Murphy on 05-12-2016 at 4:00 pm
Categories: Cadence, EDA

Mixed-signal design creates all sorts of interesting problems for implementation and verification flows, particularly when it comes to design for low power. We tend to think of mixed-signal as a few blocks like PLLs, ADCs and PHYs on the periphery of the design. Constrain and verify the digital power requirements up to analog … Read More

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Channel Operating Margin (COM) — A Standard for SI Analysis

Channel Operating Margin (COM) — A Standard for SI Analysis
by Tom Dillinger on 05-12-2016 at 12:00 pm
Categories: EDA, Siemens EDA

There’s an old adage, attributed to renowned computer scientist Andrew Tannenbaum, one that perhaps only engineers find amusing: “The nice thing about standards is that you have so many to choose from.” Nevertheless, IEEE standards arise from customer requirements in the electronics industry. Many relate… Read More

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CEO Insight: Transformation of Vayavya Labs into System Design Automation

CEO Insight: Transformation of Vayavya Labs into System Design Automation
by Pawan Fangaria on 05-12-2016 at 7:00 am
Categories: EDA

With the advent of SoCs, design abstractions and verification has moved up at the system level. It’s imperative that EDA moves up the value chain to start design automation at system level. The System Design Automation will be the new face of EDA in coming years.… Read More

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Why NXP is Moving to FD-SOI (Part II)

Why NXP is Moving to FD-SOI (Part II)
by Ron Martino on 05-10-2016 at 2:00 pm
Categories: Arm, Automotive, EDA, FD-SOI, IP

At NXP, we’re very excited about the prospects for our new i.MX 7 and 8 series of applications processors, which we’re manufacturing on 28nm FD-SOI. As noted in part I of this article series, the new i.MX 7 series, which leverages the 32-bit ARM v7-A core, is targeting the general embedded, e-reader, medical, wearable… Read More

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TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes

TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes
by Daniel Nenni on 05-10-2016 at 12:00 pm
Categories: EDA, FinFET, Solido

Being that TSMC and Solido are founding members of SemiWiki, you should be able find out everything you ever wanted to know on their respective landing pages. If not, just ask a question in the SemiWiki forum and I can assure you it will be answered in great detail. And here are some other interesting 2015 factoids from Solido:… Read More

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Why is NXP Moving to FD-SOI?

Why is NXP Moving to FD-SOI?
by Ron Martino on 05-08-2016 at 11:00 am
Categories: Arm, EDA, FD-SOI, Foundries, IP, Samsung Foundry

The latest generations of power efficient and full-featured applications processors in NXP’s very successful and broadly deployed i.MX platform are being manufactured on 28nm FD-SOI. The new i.MX 7 series leverages the 32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets, where… Read More

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One FPGA synthesis flow for different IP types

One FPGA synthesis flow for different IP types
by Don Dingee on 05-06-2016 at 4:00 pm
Categories: EDA, FPGA, Synopsys

Both Altera and Xilinx are innovative companies with robust ecosystems, right? It would be a terrible shame if you located the perfect FPGA IP block for a design, but couldn’t use it because it was in the “wrong” format for your preferred FPGA. What if there were a way around that?

There is a compelling argument to use each FPGA vendor’s… Read More

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Seven Reasons to Attend DAC in Austin

Seven Reasons to Attend DAC in Austin
by Daniel Payne on 05-06-2016 at 7:00 am
Categories: EDA, Events

I’m attending the 53rd Design Automation Conference (DAC) in Austin, Texas starting June 5th, and there are at least seven reasons that you should consider attending as well. For decades now DAC has been the premier place for all the players in our semiconductor ecosystem to get together: Academics, Commercial vendors … Read More

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Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?

Are Standard Cell Libs, Memories and Mixed-signal IP Availabe at 7nm FF?
by Eric Esteve on 05-05-2016 at 7:00 am
Categories: EDA, FinFET, IP, Synopsys

More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for… Read More