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EDA

Electronic Design Automation

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Is there anything in VLSI layout other than pushing polygons? (2)

Is there anything in VLSI layout other than pushing polygons? (2)
by Dan Clein on 10-04-2017 at 12:00 pm
Categories: Cadence, Concept Engineering, General, Siemens EDA, Synopsys

One of the important changes that happen between 1984 and 1988 is the hardware platforms development. Calma evolved, mainframe S140 with 2 combined monitors per terminal in S280 with 2 individual monitors per terminal. This meant that from noisy and darker rooms we move to more quiet and lighted rooms. We doubled the speed and the… Read More

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Photonics Summit Delivers High-Bandwidth Discussion on State of Silicon Photonics

Photonics Summit Delivers High-Bandwidth Discussion on State of Silicon Photonics
by Mitch Heins on 10-03-2017 at 12:00 pm
Categories: Cadence, EDA, Silicon Photonics

On September 6, 2017, Cadence Design Systems, Lumerical Solutions and PhoeniX Software hosted their second Photonics Summit. As with last year’s summit, this was a two-day event, with the first day including in a myriad of photonics presentations and the second day being a hands-on workshop. The hands-on workshop taught attendees… Read More

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Adoption, Architecture and Origami

Adoption, Architecture and Origami
by Bernard Murphy on 10-03-2017 at 7:00 am
Categories: Arm, Arteris, EDA, Events, IP, Oski Technology, Semiconductor Services

Last week I sat in on Oski’s latest in a series of “Decoding Formal” sessions. Judging by my first experience, they plan and manage these events very well. Not too long (~3 hours of talks), good food (DishDash), good customer content, a good forward-looking topic and a very entertaining wrap-up talk.… Read More

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TSMC Teamwork Translates to Technical Triumph

TSMC Teamwork Translates to Technical Triumph
by Tom Simon on 10-02-2017 at 12:00 pm
Categories: Foundries, IP, Siemens EDA, Silicon Creations, TSMC

Most people think that designing successful high speed analog circuits requires a mixture of magic, skill and lots of hard work. While this might be true, in reality it also requires a large dose of collaboration among each of the members of the design, tool and fabrication panoply. This point was recently made abundantly clear … Read More

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Design for Manufacturability Analysis for PCB’s

Design for Manufacturability Analysis for PCB’s
by Tom Dillinger on 09-29-2017 at 7:00 am
Categories: Cadence, EDA

Chip designers are familiar with the additional physical design checking requirements that were incorporated into flows at advanced process nodes. With the introduction of optical correction and inverse lithography technology applied during mask data generation, and with the extension of a 193nm exposure source to finer… Read More

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Emulation Methodology for Drones and Other Video-Intensive Multimedia SoCs

Emulation Methodology for Drones and Other Video-Intensive Multimedia SoCs
by Richard Pugh on 09-28-2017 at 12:00 pm
Categories: EDA, Siemens EDA

What do drones, augmented reality devices, and 4K UHD TV have in common? They all include complex system-on-chips (SoCs) that must encode and decode, in real-time, data for increasingly higher definition video content. Verifying that these SoC designs are functionally correct is quite complex, but they must also function efficiently… Read More

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High-Speed Equivalence Checking

High-Speed Equivalence Checking
by Bernard Murphy on 09-28-2017 at 7:00 am
Categories: Cadence, EDA

Following on product introductions for simulation and prototyping, physical verification and implementation earlier in the year, Anirudh Devgan (Exec VP and GM at Cadence), the king of speed and parallelism has done it again, this time with logic equivalence checking (LEC). Cadence recently announced an advance to their well-known… Read More

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Portable Stimulus Standard, What’s New from Cadence

Portable Stimulus Standard, What’s New from Cadence
by Daniel Payne on 09-27-2017 at 12:00 pm
Categories: Cadence, EDA

I’ve been hearing about the Portable Stimulus Standard (PSS) since DAC 2016, so it’s helpful to get an update from EDA vendors on what their involvement level is with this emerging standard and how they see it helping design and verification engineers. Earlier in September I scheduled a conference call with Cadence… Read More

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CDNLive Boston Keynote Address Highlights Emergence of Silicon Photonics

CDNLive Boston Keynote Address Highlights Emergence of Silicon Photonics
by Mitch Heins on 09-27-2017 at 7:00 am
Categories: Cadence, EDA, Silicon Photonics

I had the pleasure of being able to attend the CDNLive event held in the Boston, MA area last month and I was pleasantly surprised to see that Cadence highlighted Silicon Photonics as one of its Keynote topics. MIT Professor Duane Boning gave an excellent overview of the current state of silicon photonics and why he believes it is time… Read More

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How to Avoid Jeopardizing SoC Security when Implementing eSIM?

How to Avoid Jeopardizing SoC Security when Implementing eSIM?
by Eric Esteve on 09-26-2017 at 12:00 pm
Categories: EDA, IoT, Mobile, Security, Synopsys

Smart card business is now more than 25 years old, we can assess that the semiconductor industry is able to protect the chips used for smart card or SIM application with a very good level (unfortunately, it’s very difficult to get access to the fraud percentage linked with smart cards, as bankers really don’t like to communicate on… Read More