RVN! 26 Banner revised (800 x 100 px) (600 x 100 px)
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4426
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4426
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

WEBINAR: Two-Part Series on RF Power Amplifier Design

WEBINAR: Two-Part Series on RF Power Amplifier Design
by Don Dingee on 03-03-2026 at 6:00 am

VNA inspired simulated load pull setup for RF power amplifier design

At lower frequencies with simpler modulation, RF power amplifier (PA) designers could safely concentrate on a few primary metrics – like gain and bandwidth – and rely on relaxed margins to ensure proper operation in a range of conditions. Today’s advanced RF PA design is a different story. mmWave and sub-THz frequencies introduce… Read More


How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROI

How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROI
by Kalar Rajendiran on 02-26-2026 at 10:00 am

chip design for blog

As computing expands from data centers to edge devices, semiconductor designers face increasing pressure to optimize both performance and energy efficiency. Advanced process nodes continue to provide transistor-level improvements, but scaling alone cannot meet the demands of hyperscale AI infrastructure or ultra-low-power… Read More


Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic Engineering

Designing the Future: AI-Driven Multi-Die Innovation in the Era of Agentic Engineering
by Daniel Nenni on 02-25-2026 at 8:00 am

1 abhijeet chakraborty chiplet summit keynote 2026

At the 2026 Chiplet Summit, Synopsys presented a bold vision for the future of semiconductor innovation: AI-driven multi-die design powered by agentic intelligence. As the semiconductor industry shifts rapidly toward chiplet-based architectures and 3D stacking, the complexity of design, verification, and system integration… Read More


An Agentic Formal Verifier. Innovation in Verification

An Agentic Formal Verifier. Innovation in Verification
by Bernard Murphy on 02-25-2026 at 6:00 am

Innovation New

In a break from our academic-centric picks, here we look at an agentic verification flow developed within a semiconductor company. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas.… Read More


Siemens to Deliver Industry-Leading PCB Test Engineering Solutions

Siemens to Deliver Industry-Leading PCB Test Engineering Solutions
by Daniel Nenni on 02-24-2026 at 8:00 am

Siemens Acquires ASTER Technologies to Deliver Industry Leading PCB Test Engineering Solutions

Siemens has strengthened its position in EDA and manufacturing by acquiring ASTER Technologies, a specialist in test and reliability solutions for printed circuit boards. The acquisition represents a strategic step in Siemens’ broader vision to deliver a fully integrated, end-to-end digital thread for electronics design,… Read More


Agentic EDA Panel Review Suggests Promise and Near-Term Guidance

Agentic EDA Panel Review Suggests Promise and Near-Term Guidance
by Bernard Murphy on 02-24-2026 at 6:00 am

Massive AI datacenter

NetApp recently hosted a webinar on Agentic AI as the future for EDA and implications for infrastructure. Good list of panelists including Mahesh Turaga (VP Cadence Cloud) with an intro preso on infrastructure and agentic AI at Cadence, then our own Dan Nenni (Mr. SemiWiki) moderating, Khaled Heloue (Fellow AMD, CAD CAD/Methodology/AI),… Read More


Hardware is the Center of the Universe (Again)

Hardware is the Center of the Universe (Again)
by Lauro Rizzatti on 02-23-2026 at 10:00 am

Hardware is the Center of the Universe (Again) Figure 1

The 40-Year Evolution of Hardware-Assisted Verification — From In-Circuit Emulation to AI-Era Full-Stack Validation

For more than a decade, Hardware-Assisted Verification platforms have been the centerpiece of the verification toolbox. Today, no serious semiconductor program reaches tapeout without emulation or FPGA-prototyping… Read More


Smarter ECOs: Inside Easy-Logic’s ASIC Optimization Engine

Smarter ECOs: Inside Easy-Logic’s ASIC Optimization Engine
by Daniel Nenni on 02-23-2026 at 8:00 am

Easy Logic EDA

Easy-Logic Technology Ltd. is a specialized Electronic Design Automation (EDA) company focused on solving one of the most complex and time-sensitive challenges in semiconductor design: functional Engineering Change Orders (ECOs). Founded in 2014 and headquartered in Hong Kong, the company has built its reputation around

Read More

What is the 3nm Pessimism Wall and Why is it An Economic Crisis?

What is the 3nm Pessimism Wall and Why is it An Economic Crisis?
by Mike Gianfagna on 02-20-2026 at 8:00 am

What is the 3nm Pessimism Wall and Why is it An Economic Crisis?

Chip design is getting more difficult as technology advances. Everyone knows that. A lot of the discussion around these issues tends to focus on the demands posed by massive AI workloads and the challenges of shifting to heterogeneous multi-die design. While these create real problems, there is an underlying effect that is making… Read More


CEO Interview with Aftkhar Aslam of yieldWerx

CEO Interview with Aftkhar Aslam of yieldWerx
by Daniel Nenni on 02-20-2026 at 6:00 am

IMG 9364 3

Aftkhar Aslam is the Co-Founder and Chief Executive Officer of yieldWerx and a semiconductor industry veteran with more than 30 years of experience spanning manufacturing, test engineering, yield management, IP strategy, and enterprise digital transformation.

Under his leadership, yieldWerx has become a trusted data and… Read More