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Electronic Design Automation
The transition to advanced process nodes is reshaping high-speed interface IP requirements for mobile, automotive, AR/VR, and AI edge devices. As SoC designers migrate to cutting-edge foundry technologies, the demand for highly optimized MIPI PHY solutions continues to grow. A key development in this space is the availability… Read More
Engineering documentation has always been difficult to produce, maintain, and scale. But with the rise of generative AI, many organizations are asking a reasonable question: can a general-purpose large language model (LLM) like Claude automate the work? At first glance, the answer appears to be yes.
Modern LLMs can generate… Read More
With over a trillion chips manufactured every year and application requirements evolving faster than ever (across automotive, HPC, and AI), the pressure on SoC design teams has never been higher with design space keeps growing and schedules keep shrinking.
Indeed, for a complex SoC project, the number of possible configurations… Read More
The semiconductor industry is entering a transformative new phase, driven by the convergence of artificial intelligence, cloud computing, and increasingly complex chip architectures. That message took center stage during the keynote talks at the Siemens EDA User2User 2026 North America conference. Executives from Siemens,… Read More
Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close… Read More
Quick recap: verification is checking that your implementation of a design matches the in-house design/test specification. In contrast, validation means checking that the implementation matches design intent as defined by a customer specification, use cases, etc. Let’s focus on verification; for simplicity I’ll use “design… Read More
The semiconductor industry creates increasingly complex SoC and chiplets using lots of IP and all of that IP needs to be characterized at the cell level. As we design with 3nm and 2nm nodes, the sheer volume of data required for accurate static timing analysis (STA) is greatly increasing. Modern design flows rely on characterized… Read More
A single bug on a full-chip SoC can pull engineers off roadmap work for days or even weeks. It involves massive waveforms, thousands of files of RTL and UVM, and dense specs that aren’t always perfect. Finding these bugs have always been a matter of engineer-hours and how well knowledge diffuses through the organization.
Bronco … Read More
I was born in the UK (then still a part of Europe), so always eager to see them succeed. But I must admit that past behavior has reinforced the view that the EU’s only active “contribution” to progress is regulation. However this seems to be changing in multiple interesting ways. On a grand scale, the Nordic economic model is taking … Read More
At the recent TSMC Technology Symposium 2026, Siemens EDA reinforced its position as one of the key ecosystem partners supporting TSMC in the race toward AI-driven semiconductor design, advanced packaging, and next-generation process technologies. The annual forum has become one of the semiconductor industry’s most important… Read More
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Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools