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Static Timing Analysis Signoff – A comprehensive and Robust Approach

Static Timing Analysis Signoff – A comprehensive and Robust Approach
by Admin on 09-02-2025 at 6:00 am

pic2 xtalk circuit

By Zameer Mohammed

Once a chip is taped out, changes in design are not possible – Silicon is unforgiving, does not allow postproduction modifications. In contrast, software can be updated after release, but chips remain fixed. Static Timing Analysis (STA) signoff serves as a crucial safeguard against silicon failures.

In modern… Read More


eBook on Mastering AI Chip Complexity: Pathways to First-Pass Silicon Success

eBook on Mastering AI Chip Complexity: Pathways to First-Pass Silicon Success
by Admin on 09-01-2025 at 8:00 am

MArtering AI Chip Complexity Synopsys

The rapid evolution of artificial intelligence (AI) is transforming industries, from autonomous vehicles to data centers, demanding unprecedented computational power and efficiency. As highlighted in Synopsys’ guide, the global AI chip market is projected to reach $383 billion by 2032, growing at a 38% CAGR. This … Read More


Orchestrating IC verification: Harmonize complexity for faster time-to-market

Orchestrating IC verification: Harmonize complexity for faster time-to-market
by Admin on 09-01-2025 at 6:00 am

fig1 optimize ic with mjs

By Marko Suominen and Slava Zhuchenya of Siemens Digital Industries Software.

It’s often said that an orchestra without a conductor is just a collection of talented individuals making noise. The conductor’s role is to transform that potential cacophony into a unified, beautiful symphony. The same concept holds… Read More


Perforce and Siemens at #62DAC

Perforce and Siemens at #62DAC
by Daniel Payne on 08-28-2025 at 10:00 am

perforce siemens min

Wednesday was the last day at #62DAC for me and I attended an Exhibitor Session entitled, Engineering the Semiconductor Digital Thread, which featured Vishal Moondhra, VP Solutions Engineering of Perforce IPLM and Michael Munsey, VP Semiconductor Industry at Siemens Digital Industries. Instead of just talking from slides,… Read More


Synopsys Enables AI Advances with UALink

Synopsys Enables AI Advances with UALink
by Mike Gianfagna on 08-28-2025 at 6:00 am

Synopsys Enables AI Advances with UALink

The evolution of hyperscale data center infrastructure to support the processing of trillions of parameters for large language models has created some rather substantial design challenges. These massive processing facilities must scale to hundreds of thousands of accelerators with highly efficient and fast connections.… Read More


Cocotb for Verification. Innovation in Verification

Cocotb for Verification. Innovation in Verification
by Bernard Murphy on 08-27-2025 at 6:00 am

Innovation New

This time let’s see if we can stir up some lively debate. Cocotb isn’t new but it is an interesting alternative to mainstream testing methodologies. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series … Read More


Breaking out of the ivory tower: 3D IC thermal analysis for all

Breaking out of the ivory tower: 3D IC thermal analysis for all
by Admin on 08-26-2025 at 6:00 am

figure 1

Todd Burkholder and Andras Vass-Varnai, Siemens EDA

As semiconductor devices become smaller, more powerful and more densely integrated, thermal management has shifted from an afterthought to a central challenge in modern IC design. In contemporary 3D IC architectures—where multiple chiplets are stacked and closely arrayed—power… Read More


A Big Step Forward to Limit AI Power Demand

A Big Step Forward to Limit AI Power Demand
by Bernard Murphy on 08-25-2025 at 6:00 am

Power estimation

By now everyone knows that AI has become the all-consuming driver in tech and that NVIDIA GPU-based platforms are the dominant enabler of this revolution. Datacenters worldwide are stuffed with such GPUs, serving AI workloads from automatically drafting emails and summarizing meetings to auto-creating software and controlling… Read More


Free and Open Chip Design Tools: Opportunities, Challenges, and Outlook

Free and Open Chip Design Tools: Opportunities, Challenges, and Outlook
by Admin on 08-24-2025 at 10:00 am

OPen EDA Ecosystem 2025 SemiWiki

Designing semiconductor chips has traditionally been costly and controlled by a few major Electronic Design Automation (EDA) vendors—Cadence, Synopsys, and Siemens EDA who dominate with proprietary tools protected by NDAs and restrictive licenses. Fabrication also requires expensive, often export-controlled equipment.… Read More


Silvaco: Navigating Growth and Transitions in Semiconductor Design

Silvaco: Navigating Growth and Transitions in Semiconductor Design
by Admin on 08-22-2025 at 8:00 am

Silvaco Wally Rhines

Silvaco Group, Inc., a veteran player in the EDA and the TCAD space, continues to evolve amid the booming semiconductor industry. Founded in 1984 and headquartered in Santa Clara, California, Silvaco specializes in software for semiconductor process and device simulation, analog custom design, and semiconductor intellectual… Read More