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Bringing Low-Frequency Noise into Focus

Bringing Low-Frequency Noise into Focus
by Admin on 12-23-2025 at 6:00 am

1. Primarius offers a one stop RTN solution

Key takeaways

  • The challenge of acquiring high-quality, reproducible noise data becomes achievable with Primarius’ wafer-level low-frequency noise characterization solution, which is essential for advanced nodes.
  • The Primarius 981X family raises the bar for low-frequency noise measurement metrology with its unique
Read More

Podcast EP323: How to Address the Challenges of 3DIC Design with John Ferguson

Podcast EP323: How to Address the Challenges of 3DIC Design with John Ferguson
by Daniel Nenni on 12-19-2025 at 10:00 am

Daniel is joined by John Ferguson, senior director of product management for the Calibre products in the 3DIC space at Siemens EDA. He manages the vision and product offerings in the Calibre domain for 3DIC design solutions.

Dan explores the challenges of 3DIC and chiplet-based design with John, who describes the broad range of… Read More


How vHelm Delivers an Optimized Clock Network

How vHelm Delivers an Optimized Clock Network
by Mike Gianfagna on 12-19-2025 at 6:00 am

How vHelm Delivers an Optimized Clock Network

In a prior post, I discussed how the clock is no longer just another signal at advanced nodes. Indeed, it is the most critical network on the chip. An optimized clock network can be the margin of victory for your next design. But extracting these benefits is challenging. The clock network is quite sensitive, and optimization can come… Read More


Cost, Cycle Time, and Carbon aware TCAD Development of new Technologies

Cost, Cycle Time, and Carbon aware TCAD Development of new Technologies
by Daniel Nenni on 12-18-2025 at 10:00 am

image001

Our good friend Scotten Jones wrote a paper on a product that has been in joint development with Synopsys and is now available. Scott is currently President Semiconductor Manufacturing Economics and Senior Fellow at TechInsights. Scott and I have discussed this product many times and I feel it is ground breaking technology for… Read More


3D ESD verification: Tackling new challenges in advanced IC design

3D ESD verification: Tackling new challenges in advanced IC design
by Admin on 12-17-2025 at 10:00 am

fig1 3d structures

By Dina Medhat

Three key takeaways

  • 3D ICs require fundamentally new ESD verification strategies. Traditional 2D approaches cannot address the complexity and unique connections in stacked-die architectures.
  • Classifying external and internal IOs is essential for robust and cost-efficient ESD protection. Proper differentiation
Read More

Reimagining Architectural Exploration in the Age of AI

Reimagining Architectural Exploration in the Age of AI
by Bernard Murphy on 12-17-2025 at 6:00 am

Rise and Precision flow

This is not about architecting a full SoC from scratch. You already have a competitive platform, now you want to add some kind of accelerator, maybe video, audio, ML, and need to explore architectural options for how accelerator and software should be partitioned, and to optimize PPA. Now we have AI to help us optimize you’d like … Read More


S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development

S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip Development
by Daniel Nenni on 12-16-2025 at 10:00 am

cover image(1)

MachineWare, and Andes Technology today announced a collaborative co-emulation solution designed to address the increasing complexity of RISC-V-based chip design. The solution integrates MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA Prototyping Systems, and Andes’ high-performance… Read More


A Webinar About Electrical Verification – The Invisible Bottleneck in IC Design

A Webinar About Electrical Verification – The Invisible Bottleneck in IC Design
by Mike Gianfagna on 12-16-2025 at 6:00 am

A Webinar About Electrical Verification – The Invisible Bottleneck in IC Design

Electrical rule checking (ERC) is a standard part of any design flow. There is a hidden problem with the traditional approach, however. As designs grow in complexity, whether full-custom analog, mixed-signal, or advanced-node digital, the limitations of traditional ERC tools are becoming more problematic. This can lead to… Read More


Signal Integrity Verification Using SPICE and IBIS-AMI

Signal Integrity Verification Using SPICE and IBIS-AMI
by Daniel Payne on 12-15-2025 at 10:00 am

IBIS AMI min

High-speed signals enable electronic systems by using memory interfaces, SerDes channels, data center backplanes and connectivity in automobiles.  Challenges arise from signal distortions like inter-symbol interference, channel loss and dispersion effects. Multi-gigabit data transfer rates in High-Bandwidth Memory… Read More


MZ Technologies Launches Advanced Packaging Design Video Series

MZ Technologies Launches Advanced Packaging Design Video Series
by Daniel Nenni on 12-12-2025 at 6:00 am

MZ Technologies Video Series SemiWiki

In a significant move aimed at empowering semiconductor and systems-design engineers, MZ Technologies has announced the launch of a new video series focused on advanced packaging design. This initiative comes at a time when the semiconductor industry is rapidly shifting toward multi-die, 2.5D/3D integration, heterogeneous… Read More