whitepaper semiwiki ad jitter
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4385
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4385
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Verification Futures with Bronco AI Agents for DV Debug

Verification Futures with Bronco AI Agents for DV Debug
by Daniel Nenni on 01-16-2026 at 6:00 am

Bronco AI Verification Futures 2025

Verification has become the dominant bottleneck in modern chip design. As much as 70% of the overall design cycle is now spent on verification, a figure driven upward by increasing design complexity, compressed schedules, and a chronic shortage of design verification (DV) engineering bandwidth. Modern chips generate thousands… Read More


There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?

There is more to prototyping than just FPGA: See how S2C accelerates SoC Bring-Up with high productivity toolchain?
by Daniel Nenni on 01-15-2026 at 10:00 am

cover image

System-on-Chip designs continue to grow in scale and interface diversity, placing greater demands on prototype capacity, interconnect planning, and bring-up efficiency. These challenges arise not only in large multi-FPGA programs but also in smaller designs implemented on a single device or a small FPGA cluster. In all cases,… Read More


2026 Outlook with Nilesh Kamdar of Keysight EDA

2026 Outlook with Nilesh Kamdar of Keysight EDA
by Daniel Nenni on 01-13-2026 at 10:00 am

Nilesh Kamdar Show

Tell us a little bit about yourself and your company.
I’m Nilesh Kamdar, General Manager of the Keysight EDA business unit. Keysight is an S&P 500 company that provides design, emulation, and test solutions to help engineers develop and deploy faster with less risk. On the EDA side, we focus on RFMW, high-speed digital,… Read More


Verifying RISC-V Platforms for Space

Verifying RISC-V Platforms for Space
by Bernard Murphy on 01-13-2026 at 6:00 am

User making a call through a satellite

Space applications are booming, prompted by rapidly declining launch costs now attainable through commercial competition. Thanks to ventures like SpaceX, the cost to put a satellite into low earth orbit (LEO) has dropped from $20k/kg to $2k/kg today and is expected to drop further to $200/kg or lower. Plummeting costs drive … Read More


2026 Outlook with Paul Neil of Mach42

2026 Outlook with Paul Neil of Mach42
by Daniel Nenni on 01-12-2026 at 10:00 am

Paul's headshot

Tell us a little bit about yourself and your company

I’m Paul, Chief Operating Officer at Mach42. As COO, I am responsible for the business growth of Mach42, as well as driving customer success. My previous roles included VP of Product at Axelera AI, Graphcore and XMOS. I hold a PhD in Electrical Engineering and an MBA in Technology… Read More


Siemens and NVIDIA Expand Partnership to Build the Industrial AI Operating System

Siemens and NVIDIA Expand Partnership to Build the Industrial AI Operating System
by Daniel Nenni on 01-12-2026 at 6:00 am

CES 2026 Jensen Huang founder and CEO of NVIDIA Roland Busch President and CEO of Siemens AG

At CES in Las Vegas, Siemens and NVIDIA announced a major expansion of their long-standing collaboration, aiming to create what they term the “Industrial AI Operating System.” This ambitious initiative seeks to embed artificial intelligence deeply across the entire industrial value chain—from design and engineering… Read More


Automotive Digital Twins Out of The Box and Real Time with PAVE360

Automotive Digital Twins Out of The Box and Real Time with PAVE360
by Bernard Murphy on 01-07-2026 at 6:00 am

Digital twin

Digital twins are amazing technology, virtual representations mirroring a real physical system. Twin virtual models span software, electrical/electronic and mechanical subsystems, closing the loop with feedback from real physical counterparts. The virtual model calibrates against real sensing feedback gathered in … Read More


Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation

Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation
by Daniel Nenni on 01-06-2026 at 8:00 am

Acceleration of Complex RISC V Processor Verification Using Test Generation Integrated with Hardware Emulation Synopsys

The rapid evolution of RISC-V processors has introduced unprecedented verification challenges. Modern high-end RISC-V cores now incorporate complex features such as vector and hypervisor extensions, virtual memory systems, multi-level caches, advanced interrupt architectures, and multi-hart out-of-order execution.… Read More


2026 Outlook with William Wang of ChipAgents.ai

2026 Outlook with William Wang of ChipAgents.ai
by Daniel Nenni on 01-05-2026 at 10:00 am

William Wang ChipAgents SemiWiki

William Wang is a world-leading expert in artificial intelligence, specializing in generative AI and large language models. As the Founder, CEO, and Chairman of Alpha Design AI, he brings a wealth of experience from academia and industry, having previously shipped Amazon Q at Amazon AWS Bedrock

A Mellichamp Chair Professor … Read More


Revolutionizing Hardware Design Debugging with Time Travel Technology

Revolutionizing Hardware Design Debugging with Time Travel Technology
by Daniel Nenni on 01-02-2026 at 6:00 am

DVCon Europe 2025 Undo.io

In the semiconductor industry High-Level Synthesis (HLS) and SystemC have become essential tools, allowing engineers to model complex hardware designs using familiar C/C++ constructs. Yet, despite the widespread adoption of these languages, the debugging workflows in hardware development lag far behind those in software… Read More