2
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4554
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4554
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Rethinking Phase Jitter: An Algorithmic Approach to Signal Integrity

Rethinking Phase Jitter: An Algorithmic Approach to Signal Integrity
by Admin on 10-19-2026 at 8:00 am

5439ea1b 1ae1 4770 9117 ada707e8e1d3 1 all 6144

Byline: Richard Shreiner

​Modern semiconductor architectures are pushing the absolute limits of physical scaling. As data rates climb into sub-picosecond regimes across high-performance computing, 5G/6G infrastructure, and advanced AI clusters, physical layer (Layer 1) signal integrity has shifted from an engineering… Read More


Siemens and NVIDIA Accelerate Lithography for Next-Generation AI Chips

Siemens and NVIDIA Accelerate Lithography for Next-Generation AI Chips
by Daniel Nenni on 10-19-2026 at 6:00 am

Accelerating Lithography for AI Chips

Siemens has announced advances in its collaboration with NVIDIA to accelerate computational lithography, addressing a demanding step in manufacturing advanced AI semiconductors. By integrating NVIDIA’s cuLitho library with Siemens Calibre manufacturing software, the companies aim to make sophisticated photomask optimization… Read More


Design the Right Chip: Why Prototyping Has to Be Easy

Design the Right Chip: Why Prototyping Has to Be Easy
by Daniel Nenni on 10-15-2026 at 10:00 am

pic

Design the right chip. Design the chip right.

Every verification methodology in mainstream use answers the second half of that sentence and assumes the first. Simulation, emulation, formal, constrained-random testbenches, coverage closure — all of them take a specification as given and ask whether the implementation matches… Read More


Why AI Security Starts at the Chip Level

Why AI Security Starts at the Chip Level
by Daniel Nenni on 10-15-2026 at 6:00 am

Luminous Shield Over an AI Chip

Artificial intelligence is becoming part of the infrastructure that powers healthcare, transportation, finance, manufacturing, and everyday digital services. As these systems grow more capable, they also process more sensitive information and depend on increasingly complex hardware. The Synopsys white paper, “Securing… Read More


CTO Interview with Sirish Munipalli of Moores Lab AI

CTO Interview with Sirish Munipalli of Moores Lab AI
by Daniel Nenni on 10-14-2026 at 12:00 pm

Agentic AI for chip verification

Sirish Munipalli is Co-Founder and CTO of Moores Lab AI, where he leads the development of agentic AI for chip design verification, including SpecAgent(tm), the company’s specification and modeling platform. He has spent about 15 years designing and verifying complex silicon: FPGA prototyping at Intel, post-silicon validation… Read More


CTO Interview with Dr. Zakir Syed of ClockEdge

CTO Interview with Dr. Zakir Syed of ClockEdge
by Daniel Nenni on 10-12-2026 at 12:00 pm

Precision for every clock edge

Dr. Zakir Syed is Co-founder and Chief Technology Officer of ClockEdge, where he has played a central role in developing specialized simulation technology for advanced semiconductor clock networks. He brings more than 30 years of experience in electronic design automation and semiconductor verification. He joined Simplex… Read More


Overcoming the Edge AI Power Wall with Low-Voltage Foundation IP

Overcoming the Edge AI Power Wall with Low-Voltage Foundation IP
by Kalar Rajendiran on 10-12-2026 at 8:00 am

Voltage Regions and Impact of Voltage Scaling

As artificial intelligence (AI) workloads migrate to endpoint hardware, edge AI devices face immense pressure to deliver real-time inference within highly restrictive power and thermal envelopes. Traditional silicon scaling no longer yields the power-density returns it once did. To compensate, engineering teams are turning… Read More


Keysight Advances its Design Software with Agentic AI

Keysight Advances its Design Software with Agentic AI
by Daniel Nenni on 10-12-2026 at 6:00 am

AI Orchestrates RF Circuit Design

Keysight Technologies is opening a new route for artificial intelligence into radio frequency engineering. Announced on October 6, 2026, its latest software capabilities let engineers connect their own AI agents and large language models to Advanced Design System (ADS) 2027. Agents can help generate and optimize circuits,… Read More


ChipAgents and NVIDIA Put Autonomous Chip Design to the Test

ChipAgents and NVIDIA Put Autonomous Chip Design to the Test
by Daniel Nenni on 10-11-2026 at 10:00 am

ChipAgents and NVIDIA test autonomous design

ChipAgents has introduced Build-A-Chip-Bench, a benchmark developed with NVIDIA to evaluate whether AI agents can complete digital chip design tasks from specification through physical implementation. The initiative measures progress beyond generating hardware code, asking whether autonomous systems can deliver verified… Read More


Podcast EP373: The Impact of yieldHUB Live and Details of Upcoming Show Participation with Gillian O’Donnell

Podcast EP373: The Impact of yieldHUB Live and Details of Upcoming Show Participation with Gillian O’Donnell
by Daniel Nenni on 10-09-2026 at 10:00 am

Daniel is joined by Gillian O’Donnell, Director of Growth at yieldHUB, the enterprise yield management platform trusted by semiconductor and photonics manufacturers worldwide. She leads business development, marketing, PR, and partnerships, with a particular focus on yieldHUB Live, the company’s real-time… Read More