At Hot Chips 2026, OpenAI presented Jalapeño, an inference ASIC built with AI in the design loop. As reported from the session by ServeTheHome and Tom’s Hardware, OpenAI showed measured block-level wins over a human baseline — 56% on a BF16 multiply, alongside a 10% smaller matrix-unit area — within a roughly nine-month path from… Read More
Electronic Design Automation
Rethinking Phase Jitter: An Algorithmic Approach to Signal Integrity
Byline: Richard Shreiner
Modern semiconductor architectures are pushing the absolute limits of physical scaling. As data rates climb into sub-picosecond regimes across high-performance computing, 5G/6G infrastructure, and advanced AI clusters, physical layer (Layer 1) signal integrity has shifted from an engineering… Read More
Siemens and NVIDIA Accelerate Lithography for Next-Generation AI Chips
Siemens has announced advances in its collaboration with NVIDIA to accelerate computational lithography, addressing a demanding step in manufacturing advanced AI semiconductors. By integrating NVIDIA’s cuLitho library with Siemens Calibre manufacturing software, the companies aim to make sophisticated photomask optimization… Read More
Design the Right Chip: Why Prototyping Has to Be Easy
Design the right chip. Design the chip right.
Every verification methodology in mainstream use answers the second half of that sentence and assumes the first. Simulation, emulation, formal, constrained-random testbenches, coverage closure — all of them take a specification as given and ask whether the implementation matches… Read More
Why AI Security Starts at the Chip Level
Artificial intelligence is becoming part of the infrastructure that powers healthcare, transportation, finance, manufacturing, and everyday digital services. As these systems grow more capable, they also process more sensitive information and depend on increasingly complex hardware. The Synopsys white paper, “Securing… Read More
CTO Interview with Sirish Munipalli of Moores Lab AI
Sirish Munipalli is Co-Founder and CTO of Moores Lab AI, where he leads the development of agentic AI for chip design verification, including SpecAgent(tm), the company’s specification and modeling platform. He has spent about 15 years designing and verifying complex silicon: FPGA prototyping at Intel, post-silicon validation… Read More
CTO Interview with Dr. Zakir Syed of ClockEdge
Dr. Zakir Syed is Co-founder and Chief Technology Officer of ClockEdge, where he has played a central role in developing specialized simulation technology for advanced semiconductor clock networks. He brings more than 30 years of experience in electronic design automation and semiconductor verification. He joined Simplex… Read More
Overcoming the Edge AI Power Wall with Low-Voltage Foundation IP
As artificial intelligence (AI) workloads migrate to endpoint hardware, edge AI devices face immense pressure to deliver real-time inference within highly restrictive power and thermal envelopes. Traditional silicon scaling no longer yields the power-density returns it once did. To compensate, engineering teams are turning… Read More
Keysight Advances its Design Software with Agentic AI
Keysight Technologies is opening a new route for artificial intelligence into radio frequency engineering. Announced on October 6, 2026, its latest software capabilities let engineers connect their own AI agents and large language models to Advanced Design System (ADS) 2027. Agents can help generate and optimize circuits,… Read More
ChipAgents and NVIDIA Put Autonomous Chip Design to the Test
ChipAgents has introduced Build-A-Chip-Bench, a benchmark developed with NVIDIA to evaluate whether AI agents can complete digital chip design tasks from specification through physical implementation. The initiative measures progress beyond generating hardware code, asking whether autonomous systems can deliver verified… Read More


TSMC’s Patent and the Harsh Realities of 3D DRAM Competition