Synopsys’ collaboration with AMD on the Instinct MI455X GPU highlights a shift in how advanced AI processors are developed. Increasing performance depends on coordinating compute dies, memory interfaces, packaging, power delivery, and software. According to Synopsys’ announcement, AMD used its design, verification, … Read More
Electronic Design Automation
S2C Targets Faster RISC-V Bring-Up With Prototyping and AI
S2C showcased FPGA prototyping and AI-assisted debugging at the sixth RISC-V Summit China, outlining how developers can validate complex processor designs and begin software development before first silicon. Its demonstrations connected three stages of that effort: running substantial RISC-V systems on FPGA hardware,… Read More
WEBINAR: Cut down EDA License cost by 25% with Stratos AI Nitro
Expensive EDA licenses should keep chip design moving. Yet when license activity and job queues live in separate systems, teams can struggle to understand why work is waiting, which tools are underused, and whether additional spending will solve the problem. Idle seats, checkout failures, and stalled jobs can consume budgets… Read More
Beyond the Post-Mortem: How yieldHUB Live Turns the Test Floor Into an Open Window
At SEMICON West 2026 I sat down with John O’Donnell, founder and CEO, and Gillian O’Donnell, Director of Growth, to talk about how yieldHUB Live is transforming the semiconductor test floor from a blind spot into a real-time command center.
For decades, semiconductor test floors have operated as high-stakes black… Read More
Who Gets to Move the Recipe? How Autonomous Agents Earn Decision Authority in the Fab
by Ajay Kumar Govindaram
There’s a question I’ve started asking at every agentic AI demo I sit through, and it has a clean answer in every fab on earth: who is allowed to change the recipe? In a semiconductor factory, that was settled decades ago. A person doesn’t touch a production recipe because they feel confident.… Read More
Moving Beyond AI-Assisted Design – Agentrys Shows the Way with Agentic Loop Engineering
At Hot Chips 2026, OpenAI presented Jalapeño, an inference ASIC built with AI in the design loop. As reported from the session by ServeTheHome and Tom’s Hardware, OpenAI showed measured block-level wins over a human baseline — 56% on a BF16 multiply, alongside a 10% smaller matrix-unit area — within a roughly nine-month path from… Read More
Rethinking Phase Jitter: An Algorithmic Approach to Signal Integrity
Byline: Richard Shreiner
Modern semiconductor architectures are pushing the absolute limits of physical scaling. As data rates climb into sub-picosecond regimes across high-performance computing, 5G/6G infrastructure, and advanced AI clusters, physical layer (Layer 1) signal integrity has shifted from an engineering… Read More
Siemens and NVIDIA Accelerate Lithography for Next-Generation AI Chips
Siemens has announced advances in its collaboration with NVIDIA to accelerate computational lithography, addressing a demanding step in manufacturing advanced AI semiconductors. By integrating NVIDIA’s cuLitho library with Siemens Calibre manufacturing software, the companies aim to make sophisticated photomask optimization… Read More
Design the Right Chip: Why Prototyping Has to Be Easy
Design the right chip. Design the chip right.
Every verification methodology in mainstream use answers the second half of that sentence and assumes the first. Simulation, emulation, formal, constrained-random testbenches, coverage closure — all of them take a specification as given and ask whether the implementation matches… Read More
Why AI Security Starts at the Chip Level
Artificial intelligence is becoming part of the infrastructure that powers healthcare, transportation, finance, manufacturing, and everyday digital services. As these systems grow more capable, they also process more sensitive information and depend on increasingly complex hardware. The Synopsys white paper, “Securing… Read More


Intel’s Tiny Bridges Could Lead to Very Big Paychecks