Easy-Logic, a leading provider of high-performance Engineering Change Order (ECO) solutions in Electronic Design Automation (EDA), will showcase its latest innovation — the EasyAI ECO Suite — at DAC in Los Angeles, July 27–29, 2026. This intelligent ECO solution integrates AI engines into the entire ECO workflow and systematically… Read More
Electronic Design Automation
From Detection to Safety: Reframing Fault Simulation for Functional Safety
In the early 1980s, when computer-aided engineering (CAE), the precursor to modern electronic design automation (EDA), was just taking shape, my professional trajectory shifted in a way that would prove foundational. I joined Teradyne, the Boston-based leader in automated test equipment (ATE), and I encountered for the first… Read More
Podcast EP353: What Real-Time Visibility Is and Why it Matters with yieldHUB’s John O’Donnell
Daniel is joined by John O’Donnell, Founder and CEO of yieldHUB, a pioneering leader in advanced data analytics for the semiconductor industry. Since establishing the company in 2005 he has transformed it from a two-person startup into a trusted multinational partner that empowers some of the world’s leading semiconductor … Read More
Foundation IP for Intel 18A: Technical Overview and Why It Matters
Synopsys Foundation IP for Intel 18A is a portfolio of semiconductor building blocks designed to help system-on-chip developers build advanced chips with better power, performance, and area, often called PPA. The offering includes embedded memory compilers, standard-cell logic libraries, and input/output libraries for… Read More
WEBINAR: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools
The real promise of AI in EDA is not to replace EDA tools or reinvent design flows, it is to help engineers accomplish existing tasks even more complex design tasks faster, more safely, and with far less tool expertise than was previously required.
The webinar explores what a truly effective AI-powered EDA tool should look like, … Read More
Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test
Even with advances in AI, automation, and advanced process technology, many semiconductor test operations still rely on reports generated hours after production has occurred. This creates a significant and growing problem. By the time engineers discover a yield excursion, parametric drift, tester issue, or an increase in… Read More
Improving Verification of Battery Cell Monitoring Chips
Batteries, especially for electric vehicles, are very much in the news these days. This technology is vital for many aspects of our modern lives, but people often worry about things like range limitations and the possibility of overheating. The industry is responding with electronic solutions for improving battery operation.… Read More
Enhancing Multi-Domain System Simulation with FMI Co-Simulation
As systems become increasingly complex across every field of science and engineering, the importance of computer simulation in design, analysis, and verification continues to increase over time. The traditional process in which a system is modeled and simulated in a single tool is called monolithic simulation. On the other… Read More
Applying QED to Hardware Accelerator Verification. Innovation in Verification
QED (Quick Error Detection) can be a powerful complementary addition to verification but can be subject to size constraints. This month’s paper looks at a fix for that limitation. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More
When Software Outruns Silicon: Hardware-Assisted Test Generation to the Rescue
For the past decade, the semiconductor industry has been moving in one direction: shift-left, specifically, shifting more validation into the pre-silicon phase. The idea was straightforward: if software ultimately determines how a system behaves, then software should become a primary vehicle for verification.
The industry… Read More


Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?