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Beyond Workflow Agents: Toward Design Intelligence in Analog EDA

Beyond Workflow Agents: Toward Design Intelligence in Analog EDA
by ChandraM on 07-09-2026 at 6:00 am

ChandraM LongPost AgenticStack

Over the last year, the EDA industry has started using a new vocabulary: agents, super agents, mental models, native skills, playbooks, RAG, MCP, autonomous workflows, and AI-first design.

The language is new, but the motivation is familiar to anyone who has worked in chip design.

Design complexity keeps increasing. The number… Read More


MooresLabAI at DAC 2026: Why the Future of Semiconductor Engineering Is Agentic, Not Just Generative

MooresLabAI at DAC 2026: Why the Future of Semiconductor Engineering Is Agentic, Not Just Generative
by Daniel Nenni on 07-08-2026 at 2:00 pm

DAC MLAI BuildingTheFuture

For decades, semiconductor innovation has been constrained not by imagination, but by engineering capacity. While transistor density has continued to advance, the process of building chips has remained fundamentally manual, fragmented across specifications, RTL, verification, debugging, coverage analysis, and signoff.… Read More


IP Lifecycle Management in the AI Era

IP Lifecycle Management in the AI Era
by Bernard Murphy on 07-08-2026 at 6:00 am

designer trying to find best IP options in a tangle of choices

Large design enterprises have multiple concurrent activities around IP of various types: software/firmware, blocks defined in RTL or HLS, verification IPs of multiple different types, physical implementations, scripts/files for timing, power management, etc., etc. Each of these continues to evolve and branch to serve … Read More


See Autonomous Chip Design in Action with ChipAgents at DAC 2026

See Autonomous Chip Design in Action with ChipAgents at DAC 2026
by Daniel Nenni on 07-07-2026 at 2:00 pm

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Making the AI wave at DAC 2026 in Long Beach

DAC comes to Long Beach for the first time in 2026, with artificial intelligence expected to be one of the central topics across the conference program and exhibition floor.

For semiconductor design and verification teams, the discussion has moved beyond whether AI can assist engineers.… Read More


Demonstrating the EasyAI ECO Suite – An AI-Powered Functional ECO Solution at DAC 2026

Demonstrating the EasyAI ECO Suite – An AI-Powered Functional ECO Solution at DAC 2026
by Daniel Nenni on 07-07-2026 at 6:00 am

EasylogicECO AI Driven ECO Solution

Easy-Logic, a leading provider of high-performance Engineering Change Order (ECO) solutions in Electronic Design Automation (EDA), will showcase its latest innovation — the EasyAI ECO Suite — at 2026 DAC in Los Angeles, July 27–29, 2026. This intelligent ECO solution integrates AI engines into the entire ECO workflow and systematically… Read More


From Detection to Safety: Reframing Fault Simulation for Functional Safety

From Detection to Safety: Reframing Fault Simulation for Functional Safety
by Lauro Rizzatti on 07-06-2026 at 10:00 am

From Detection to Safety Figure 1

In the early 1980s, when computer-aided engineering (CAE), the precursor to modern electronic design automation (EDA), was just taking shape, my professional trajectory shifted in a way that would prove foundational. I joined Teradyne, the Boston-based leader in automated test equipment (ATE), and I encountered for the firstRead More


Podcast EP353: What Real-Time Visibility Is and Why it Matters with yieldHUB’s John O’Donnell

Podcast EP353: What Real-Time Visibility Is and Why it Matters with yieldHUB’s John O’Donnell
by Daniel Nenni on 07-03-2026 at 2:00 pm

Daniel is joined by John O’Donnell, Founder and CEO of yieldHUB, a pioneering leader in advanced data analytics for the semiconductor industry. Since establishing the company in 2005 he has transformed it from a two-person startup into a trusted multinational partner that empowers some of the world’s leading semiconductor … Read More


Foundation IP for Intel 18A: Technical Overview and Why It Matters

Foundation IP for Intel 18A: Technical Overview and Why It Matters
by Daniel Nenni on 07-03-2026 at 6:00 am

Intel 18A Foundation IP Synopsys

Synopsys Foundation IP for Intel 18A is a portfolio of semiconductor building blocks designed to help system-on-chip developers build advanced chips with better power, performance, and area, often called PPA. The offering includes embedded memory compilers, standard-cell logic libraries, and input/output libraries for… Read More


WEBINAR: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools

WEBINAR: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools
by Daniel Nenni on 07-02-2026 at 2:00 pm

webinar square AI 2026 v2

The real promise of AI in EDA is not to replace EDA tools or reinvent design flows, it is to help engineers accomplish existing tasks even more complex design tasks faster, more safely, and with far less tool expertise than was previously required.

The webinar explores what a truly effective AI-powered EDA tool should look like, … Read More


Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test

Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test
by Mike Gianfagna on 07-02-2026 at 6:00 am

Why Real Time Intelligence is the Next Differentiator in Semiconductor Test

Even with advances in AI, automation, and advanced process technology, many semiconductor test operations still rely on reports generated hours after production has occurred. This creates a significant and growing problem. By the time engineers discover a yield excursion, parametric drift, tester issue, or an increase in… Read More