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WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4171
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4171
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping

Unlocking SoC Debugging Challenges: Paving the Way for Efficient Prototyping
by Daniel Nenni on 10-21-2024 at 10:00 am

3D rendering of cyberpunk AI. Circuit board. Technology background. Central Computer Processors CPU and GPU concept. Motherboard digital chip. Tech science background.

As chip design complexity increases, integration scales expand and time-to-market pressures grow, as a result, design verification has become increasingly challenging. In multi-FPGA environments, the complexity of design debugging and verification further escalates, making it difficult for traditional debugging methods… Read More


Prioritize Short Isolation for Faster SoC Verification

Prioritize Short Isolation for Faster SoC Verification
by Ritu Walia on 10-17-2024 at 10:00 am

Fig1 shorts analysis conf data

Improve productivity by shifting left LVS
In modern semiconductor design, technology nodes continue to shrink and the complexity and size of circuits increase, making layout versus schematic (LVS) verification more challenging. One of the most critical errors designers encounter during LVS runs are shorted nets. Identifying… Read More


The Perils of Aging, From a Semiconductor Device Perspective

The Perils of Aging, From a Semiconductor Device Perspective
by Mike Gianfagna on 10-17-2024 at 6:00 am

The Perils of Aging, From a Semiconductor Device Perspective

We‘re all aware of the challenges aging brings. I find the older I get, the more in touch I feel with those challenges.  I still find it to be true that aging beats the alternative. I think most would agree. Human factors aside, I’d like to discuss the aging process as applied to the realm of semiconductor device physics. Here, as with… Read More


Navigating Resistance Extraction for the Unconventional Shapes of Modern IC Designs

Navigating Resistance Extraction for the Unconventional Shapes of Modern IC Designs
by Nada Tarek on 10-15-2024 at 6:00 am

Fig1 MEMS design

The semiconductor industry is experiencing rapid evolution, driven by the proliferation of IoT applications, image sensors, photonics, MEMS applications, 3DIC and other emerging technologies. This growth has dramatically increased the complexity of integrated circuit (IC) design. One aspect of this complexity is the … Read More


Hearing Aids are Embracing Tech, and Cool

Hearing Aids are Embracing Tech, and Cool
by Bernard Murphy on 10-14-2024 at 6:00 am

earbud2a min

You could be forgiven for thinking of hearing aids as the low end of tech, targeted to a relatively small and elderly audience. Commercials seem unaware of advances in mobile consumer audio, and white-haired actors reinforce the intended audience. On the other hand, the World Health Organization has determined that at least 6%… Read More


CEO Interview: Tobias Ludwig of LUBIS EDA

CEO Interview: Tobias Ludwig of LUBIS EDA
by Daniel Nenni on 10-11-2024 at 6:00 am

IMG 3442 eh

Tobias began his journey with a strong academic foundation in electronic design automation, studying at a leading university in Germany that specialized in formal verification. After graduating, Tobias gained hands-on experience in the semiconductor industry, where he quickly recognized the challenges and inefficiencies… Read More


Webinar: When Failure in Silicon Is Not an Option

Webinar: When Failure in Silicon Is Not an Option
by Daniel Nenni on 10-10-2024 at 6:00 am

background (4)

If the thought of a silicon respin keeps you awake at night, you’re not alone. Re-fabricating a chip can cost tens of millions of dollars. An unplanned respin also risks a delay in getting a product to market, which adds tremendous costs in terms of lost business.

Undoubtedly, adding to your sleep loss is the recent rise in respins.… Read More


Maximizing 3DIC Design Productivity with 3DBlox: A Look at TSMC’s Progress and Innovations in 2024

Maximizing 3DIC Design Productivity with 3DBlox: A Look at TSMC’s Progress and Innovations in 2024
by Kalar Rajendiran on 10-08-2024 at 10:00 am

3DFabric Silicon Validated Thermal Analysis

At the 2024 TSMC OIP Ecosystem Forum, one of the technical talks by TSMC focused on maximizing 3DIC design productivity and rightfully so. With rapid advancements in semiconductor technology, 3DICs have become the next frontier in improving chip performance, energy efficiency, and density. TSMC’s focus on streamlining the… Read More


The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)

The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)
by Lauro Rizzatti on 10-03-2024 at 10:00 am

Immensity of SW development Part 3 Figure 1

Part 3 of this 4-part series analyzes methods and tools involved in debugging software at different layers of the software stack.

Software debugging involves identifying and resolving issues ranging from functional misbehaviors to crashes. The essential requirement for validating software programs is the ability to monitor… Read More


SystemVerilog Functional Coverage for Real Datatypes

SystemVerilog Functional Coverage for Real Datatypes
by Mariam Maurice on 10-03-2024 at 6:00 am

fig 1

Functional coverage acts as a guide to direct verification resources by identifying the tested and untested portions of a design. Functional coverage is a user-defined metric that assesses the extent to which the design specification, as listed by the test plan’s features, has been used. It can be used to estimate the presence… Read More