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Cadence – Defining a Roadmap to the Future

Cadence – Defining a Roadmap to the Future
by Mike Gianfagna on 04-16-2020 at 10:00 am

Screen Shot 2020 04 08 at 7.46.46 PM

Cadence recently published a position paper that details a set of enabling technologies that will be needed for product design going forward. Entitled Intelligent System Design, the piece describes the changing landscape of system design and the requirements for success. Cadence has built a branded approach to address these… Read More


Breker Tips a Hat to Formal Graphs in PSS Security Verification

Breker Tips a Hat to Formal Graphs in PSS Security Verification
by Bernard Murphy on 04-16-2020 at 6:00 am

Breker security tables

It might seem paradoxical that simulation (or equivalent dynamic methods) might be one of the best ways to run security checks. Checking security is a problem where you need to find rare corners that a hacker might exploit. In dynamic verification, no matter how much we test we know we’re not going to cover all corners, so how can it… Read More


Project-Centric Design Process, or IP-centric

Project-Centric Design Process, or IP-centric
by Daniel Payne on 04-14-2020 at 10:00 am

projects

How do most IC design teams organize their work during the design process?

Most design teams would say that they organize their work into a project-centric view, and that at the beginning of the process use a tool for requirements management, maybe a bug tracker, or some design management tool. On the four IC designs that I worked … Read More


Innovation in Verification April 2020

Innovation in Verification April 2020
by Bernard Murphy on 04-14-2020 at 6:00 am

Innovation

This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea we appreciated and suggest opportunities to further build on that idea.

We’re getting a lot of hits on these blogs but would like really like to get feedback also.

The Innovation

Our next pick… Read More


Webinar on Transient Simulation of Power Transistors in Converter Circuits

Webinar on Transient Simulation of Power Transistors in Converter Circuits
by Tom Simon on 04-13-2020 at 6:00 am

PTM TR high side low side currents 300x182 1

Magwel is offering a webinar that takes a deeper look at how Power Transistors can be more accurately simulated in converter circuits to provide extremely accurate information about switching efficiency. DC converter circuit efficiency has a big effect on the battery life of mobile devices and can affect performance and efficiency… Read More


Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs

Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs
by Herb Reiter on 04-10-2020 at 6:00 am

2d 3d Semiconductor Packaging SemiWiki Cadence

I had the opportunity to preview the upcoming SemiWiki webinar titled: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs. John Park’s message, describing this powerful Cadence solution, really impressed me. That’s why I want to encourage you to register for it and join this SemiWiki … Read More


Learning to Live with the Gaps Between Design and Verification

Learning to Live with the Gaps Between Design and Verification
by Tom Simon on 04-09-2020 at 6:00 am

Learning to live with the gaps between design and verification

Whenever I am asked to explain how chip design works by someone who is unfamiliar with the process, I struggle to explain the different steps in the flow. It also makes me aware of the discrete separations between each phase of activities. Of course, when you speak to a novice it is not even possible to get more than one layer down in the… Read More


Best Practices for IP Reuse

Best Practices for IP Reuse
by Bernard Murphy on 04-08-2020 at 6:00 am

Reuse

As someone who was heavily involved with rules for IP reuse for many years, I have a major sense of déja vu in writing again on the topic. But we (in SpyGlass) were primarily invested in atomic-level checks in RTL and gate-level designs. There’s a higher level of best practices in process we didn’t attempt to cover. ClioSoft just released… Read More


Synopsys is Changing the Game with Next Generation 64-Bit Embedded Processor IP

Synopsys is Changing the Game with Next Generation 64-Bit Embedded Processor IP
by Mike Gianfagna on 04-07-2020 at 6:00 am

ARC HS5x HS6x block diagram

Synopsys issued a press release this morning that has some important news – Synopsys Introduces New 64-bit ARC Processor IP Delivering Up to 3x Performance Increase for High-End Embedded Applications. At first glance, one could assume this is just an announcement for some new additions to the popular ARC processor family. While… Read More


What’s New in CDC Analysis?

What’s New in CDC Analysis?
by Bernard Murphy on 04-06-2020 at 6:00 am

Validating assumptions in CDC constraints

Synopsys just released a white paper, a backgrounder on CDC. You’ve read enough of what I’ve written on this topic that I don’t need to re-tread that path. However, this is tech so there’s always something new to talk about. This time I’ll cover a Synopsys survey update on numbers of clock domains in designs, also an update on ways to… Read More