WP_Term Object
(
    [term_id] => 121
    [name] => IROC Technologies
    [slug] => iroc-technologies
    [term_group] => 0
    [term_taxonomy_id] => 121
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 16
    [filter] => raw
    [cat_ID] => 121
    [category_count] => 16
    [category_description] => 
    [cat_name] => IROC Technologies
    [category_nicename] => iroc-technologies
    [category_parent] => 157
    [is_post] => 
)
            
banner2
WP_Term Object
(
    [term_id] => 121
    [name] => IROC Technologies
    [slug] => iroc-technologies
    [term_group] => 0
    [term_taxonomy_id] => 121
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 16
    [filter] => raw
    [cat_ID] => 121
    [category_count] => 16
    [category_description] => 
    [cat_name] => IROC Technologies
    [category_nicename] => iroc-technologies
    [category_parent] => 157
    [is_post] => 
)

SOCFIT, Circuit Level Soft Error Analysis

SOCFIT, Circuit Level Soft Error Analysis
by Paul McLellan on 05-13-2013 at 2:50 pm

I blogged recently about reliability testing with high energy neutron beams. This is good for getting basic reliability data but it is not really a useful tool for worrying about reliability while the chip is still being designed and something can be done about it.

That is where IROC Technologies SOCFIT tool comes in. It takes all… Read More


How to Blast Your Chip with High Energy Neutron Beams

How to Blast Your Chip with High Energy Neutron Beams
by Paul McLellan on 05-06-2013 at 3:49 pm

So you want to know how reliable your chips are and how susceptible they are to single event effects (SEEs) where a neutron or an alpha particle causes a storage element (flop or memory cell) to flip in a way that alters the behavior of the device. There are two ways a particle hitting a device might not cause a problem. Firstly, the particle… Read More


Cell Level Reliability

Cell Level Reliability
by Paul McLellan on 04-03-2013 at 6:06 pm

I blogged last month about single event effects (SEE) where a semiconductor chip behaves incorrectly due to being hit by an ion or a neutron. Since we live on a radioactive planet and are bombarded by cosmic rays from space, this is a real problem, and it is getting worse at each process node. But just how big of a problem is it?


TFIT is … Read More


Reliability is the New Power

Reliability is the New Power
by Paul McLellan on 03-09-2013 at 9:56 am

It has be come a cliche to say that “power is the new timing”, the thing that keeps designers up at night and drives the major architectural decisions in big SoCs. Nobody is saying it yet but perhaps “reliability is the new power” will be tomorrow’s received wisdom.

I talked to Adrian Evans of IROCTech… Read More


We Live on a Radioactive Planet

We Live on a Radioactive Planet
by Paul McLellan on 03-01-2013 at 1:45 pm

Often as we move down the process node treadmill, new challenges appear that we didn’t really have to worry about before. Often, these challenges require addressing at a number of different levels: the process, the cell libraries, the design, the EDA tools that we use.

One well known example is the problem of metal migration.… Read More


Soft Error Rate (SER) Prediction Software for IC Design

Soft Error Rate (SER) Prediction Software for IC Design
by Daniel Payne on 04-16-2012 at 10:00 am

My first IC design in 1978 was a 16Kb DRAM chip at Intel and our researchers discovered the strange failure of Soft Errors caused by Alpha particles in the packaging and neutron particles which are more prominent at higher altitudes like in Denver, Colorado. Before today if you wanted to know the Soft Error Rate (SER) you had to fabricate… Read More