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October 14, 2019October 12, 2019

Response to IP’s Growing Impact On Yield And Reliability

Response to IP’s Growing Impact On Yield And Reliability
by Daniel Nenni on 10-14-2019 at 6:00 am
Categories: EDA, Fractal Technologies, IP
1 Comment

One of the reasons I founded SemiWiki nine years ago was the lack of EDA, IP and Foundry content in the media. The problem is that unless you work in the industry it is very difficult to write about it in competent technical detail. Most media outlets only know what vendors tell them which is how the semiconductor industry worked before… Read More

July 8, 2019July 12, 2019

Early IP Block Error Detection is Critical!

Early IP Block Error Detection is Critical!
by Daniel Nenni on 07-08-2019 at 10:00 am
Categories: EDA, Fractal Technologies, IP

Image RemovedThe rising complexity of modern SoC designs, as enabled by progressing manufacturing technology, leads to an increasing validation challenge as the only way to manage complexity increase is by re-using more pre-designed IP blocks. These IP-blocks are provided by various suppliers such as a foundry partner, internal… Read More

October 10, 2018

Crossfire Baseline Checks for Clean IP Part II

Crossfire Baseline Checks for Clean IP Part II
by Daniel Nenni on 10-10-2018 at 7:00 am
Categories: EDA, Fractal Technologies

In our previous article bearing the same title, we discussed the recommended baseline checks covering cell and pin presence, back-end, and some front-end checks related to functional equivalency. In this article, we’ll cover the extensive list of characterization checks, that include timing arcs, NLDM, CCS, ECSM/EM, and … Read More

September 26, 2018

Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm
Categories: EDA, Fractal Technologies, IP, TSMC

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where… Read More

July 9, 2018

55DAC Trip Report IP Quality

55DAC Trip Report IP Quality
by Daniel Nenni on 07-09-2018 at 7:00 am
Categories: EDA, Events, Fractal Technologies

This year I signed books in the Fractal booth (compliments of Fractal) and let me tell you it was quite an experience. IP quality is a very touchy subject and the source of many more tape-out delays than I had imagined. As it turns out, commercial IP is the biggest offender which makes no sense to me whatsoever. Even more shocking, one… Read More

June 18, 2018

Fractal Technologies Joins TSMC Open Innovation Platform EDA Alliance

Fractal Technologies Joins TSMC Open Innovation Platform EDA Alliance
by Daniel Nenni on 06-18-2018 at 7:00 am
Categories: EDA, Fractal Technologies

Image RemovedIn case you missed it, Fractal is now officially part of the TSMC EDA Alliance. Fractal Crossfire is the leading IP and Library QA tool used by TSMC and many of TSMC’s customers so this is for the greater IP good, absolutely. Fractal has also released a new white paper “Setup Generation for Fractal Crossfire” that we can… Read More

May 25, 2018

Webinar: IP Quality is a VERY Serious Problem

Webinar: IP Quality is a VERY Serious Problem
by Daniel Nenni on 05-25-2018 at 12:00 pm
Categories: EDA, Fractal Technologies
3 Comments

We just completed a run through of the upcoming IP & Library QA webinar that I am moderating with Fractal and let me tell you it is a must see for management level Semiconductor Design and Semiconductor IP companies as well as the Foundries. Seriously, if you are an IP company you had better be up on the latest QA checks if you want … Read More

May 8, 2018

Cross View Static Validation

Cross View Static Validation
by Alex Tan on 05-08-2018 at 12:00 pm
Categories: EDA, Fractal Technologies

Image Removed Improper handling of design validation could simply translate into a debugging exercise. In mainstream RTL2GDS flow, design implementation involves a top-level integration and lower-level block developments. These lower-level components, comprising of macros, IPs and standard cells are subjected to frequent… Read More

February 28, 2018

CEO Interview: Rene Donkers of Fractal Technologies

CEO Interview: Rene Donkers of Fractal Technologies
by Daniel Nenni on 02-28-2018 at 7:00 am
Categories: EDA, FinFET, Fractal Technologies

We (SemiWiki) have been working with Fractal for close to five years now publishing 25 blogs that have garnered more than 100,000 views. Generally speaking QA people are seen as the unsung heroes of EDA since the only time you really hear about them is when something goes wrong and a tapeout is delayed or a chip is respun.

FinFETs really… Read More

October 26, 2017

Good Library Hygiene Takes More Than an Occasional Scrub

Good Library Hygiene Takes More Than an Occasional Scrub
by Bernard Murphy on 10-26-2017 at 7:00 am
Categories: EDA, Fractal Technologies
1 Comment

You don’t shower only before you have to go to an important meeting (teenagers excepted). Surgical teams go further, demanding a strict regimen of hygiene be followed before anyone is allowed into an operating room. Yet we tend to assume that libraries and physical IP (analog, memories, other physical blocks) are checked and pronounced… Read More

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Recent Article Comments

Why is Intel still short on chips?
Dec 2018 Intel 'backported' the B360 PCH from 14nm to 22nm and callid it "B365", possibly to free up 14nm…

— hkwint on December 6, 2019
Evolving Landscape of Self-Driving Safety Standards
Nice article, Bernard!! Making an autonomous car perfectly safe is a tough, tough job. Probably impossible. But …. given our…

— John East on December 5, 2019
2020 Semiconductor Foundry Landscape Update!
For years Intel used a process advantage to maintain their lead on AMD. Now, using TSMC, AMD has turned the…

— John East on December 5, 2019
Is the ASIC Business Dead?
I work for an ASIC company, or perhaps more specifically IC design services company with some focus on mixed signal…

— Peter Deutschman on December 5, 2019
Why is Intel still short on chips?
Dumb as a door stop sounds more likely to me... Intel CPUs are not only made on a CPU-tailored process…

— IanD on December 4, 2019
Why is Intel still short on chips?
Yes and lets not forget this gem: Oct 22, 2018 by Charlie Demerjian SemiAccurate has learned that Intel just pulled…

— Daniel Nenni on December 3, 2019
Why is Intel still short on chips?
Clearly, but why so many articles saying otherwise? Intentional or are the editors dumb as a door stop? https://www.techradar.com/news/intel-turns-to-samsung-for-help-keeping-up-with-amd-rumor-claims https://wccftech.com/intel-has-tapped-samsung-foundries-to-manufacture-cpus/…

— Daniel Nenni on December 3, 2019
Why is Intel still short on chips?
There's this https://www.forbes.com/sites/moorinsights/2019/12/03/aws-goes-all-in-on-arm-based-graviton2-processors-with-ec2-6th-gen-instances/ We'll see if graviton2 will be commercially available. Intel may not have this problem for much longer…

— Portland on December 3, 2019
Why is Intel still short on chips?
Big Intel is too slow on ramping up, why was F42 so slow?Is it Really Up? And older Fabs still…

— kgoncher on December 3, 2019
Why is Intel still short on chips?
It was from Charlie Demerjian from semiaccurate. The guy makes a lot of claims from speculations. Honest I thought what…

— Portland on December 3, 2019

Response to IP’s Growing Impact On Yield And Reliability

Early IP Block Error Detection is Critical!

Crossfire Baseline Checks for Clean IP Part II

Crossfire Baseline Checks for Clean IP at TSMC OIP

55DAC Trip Report IP Quality

Fractal Technologies Joins TSMC Open Innovation Platform EDA Alliance

Webinar: IP Quality is a VERY Serious Problem

Cross View Static Validation

CEO Interview: Rene Donkers of Fractal Technologies

Good Library Hygiene Takes More Than an Occasional Scrub

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EARLY IP BLOCK ERROR DETECTION IS CRITICAL!

DRIVING A GLOBAL EDA INDUSTRY TRANSCENDENCE

THE SILICON REVIEW: 50 LEADING COMPANIES OF 2018

IP & LIBRARY QA WITH CROSSFIRE PRESENTATION VIDEO

CROSSFIRE BASELINE CHECKS FOR CLEAN IP PART II

FRACTAL TECHNOLOGIES LISTED ON TOP 20

Recent Article Comments

Why is Intel still short on chips?

Evolving Landscape of Self-Driving Safety Standards

2020 Semiconductor Foundry Landscape Update!

Is the ASIC Business Dead?

Why is Intel still short on chips?

Why is Intel still short on chips?

Why is Intel still short on chips?

Why is Intel still short on chips?

Why is Intel still short on chips?

Why is Intel still short on chips?