WP_Term Object
(
    [term_id] => 58
    [name] => Defacto Technologies
    [slug] => defacto-technologies
    [term_group] => 0
    [term_taxonomy_id] => 58
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 16
    [filter] => raw
    [cat_ID] => 58
    [category_count] => 16
    [category_description] => 
    [cat_name] => Defacto Technologies
    [category_nicename] => defacto-technologies
    [category_parent] => 157
    [is_post] => 
)
            
defacto banner 2020
WP_Term Object
(
    [term_id] => 58
    [name] => Defacto Technologies
    [slug] => defacto-technologies
    [term_group] => 0
    [term_taxonomy_id] => 58
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 16
    [filter] => raw
    [cat_ID] => 58
    [category_count] => 16
    [category_description] => 
    [cat_name] => Defacto Technologies
    [category_nicename] => defacto-technologies
    [category_parent] => 157
    [is_post] => 
)

RTL Correct by Construction

RTL Correct by Construction
by Bernard Murphy on 05-31-2017 at 7:00 am

Themes in EDA come in waves and a popular theme from time to time is RTL signoff. That’s a tricky concept; you can’t signoff RTL in the sense of never having to go back and change the RTL. But the intent is still valuable – to get the top-level or subsystem-level RTL as well tested as possible, together with collateral data (SDC, UPF, etc)… Read More


CEO Interview: Chouki Aktouf of Defacto Technologies

CEO Interview: Chouki Aktouf of Defacto Technologies
by Daniel Nenni on 11-14-2016 at 7:00 am

As a 30+ year semiconductor veteran I can tell you with 100% certainty that start-ups are the lifeblood of EDA. The mantra is “Innovate or Die!” and that is exactly what Defacto is doing. After more than 10 years of innovating in Design for Test at RTL, Defacto is now offering a complete EDA solution based on generic EDA… Read More


Achieving Lower Power through RTL Design Restructuring (webinar)

Achieving Lower Power through RTL Design Restructuring (webinar)
by Daniel Payne on 10-18-2016 at 4:00 pm

webinar semiwiki small

From a consumer viewpoint I want the longest battery life from my electronic devices: iPad tablet, Galaxy Note 4 smart phone, Garmin Edge 820 bike computer, and Amazon Kindle book reader. In September I blogged about RTL Design Restructuring and how it could help achieve lower power, and this month I’m looking forward to … Read More


RTL Design Restructuring Explained

RTL Design Restructuring Explained
by Daniel Payne on 09-22-2016 at 4:00 pm

Modern SoC designs can use billions of transistors where transistors are grouped into gates, then gates grouped into cells, then cells grouped into blocks, blocks grouped into modules, and so on, creating a complex hierarchy. What a front-end designer conceives of logically for a hierarchy will differ from how an optimized physical… Read More


A Versatile Design Platform with Multi-Language APIs

A Versatile Design Platform with Multi-Language APIs
by Pawan Fangaria on 04-19-2016 at 7:00 am

In one of my whitepapers “SoCs in New Context – Look beyond PPA”, I had mentioned about several considerations which have become very important in addition to power, performance, and area (PPA) of an SoC. This whitepaper was also posted in parts as blogs on Semiwiki (links are mentioned below). Two important… Read More


A Brief History of Defacto Technologies

A Brief History of Defacto Technologies
by Pawan Fangaria on 03-04-2016 at 7:00 am

In early 2000s, semiconductor design at RTL level was gaining momentum. The idea was to process more design steps such as insertion of test and other design structures upfront at the RTL level. The design optimization and verification were to be done at the RTL level to reduce long iterations through gate level design because changes… Read More